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參數(shù)資料
| 型號： | CS98ULPA877AHLF-T |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | 1.8V Low-Power Wide-Range Frequency Clock Driver |
| 中文描述： | 1.8V的低功耗寬范圍頻率時鐘驅(qū)動器 |
| 文件頁數(shù)： | 1/14頁 |
| 文件大小： | 172K |
| 代理商： | CS98ULPA877AHLF-T |
Integrated
Circuit
Systems, Inc.
ICS98ULPA877A
Advance Information
1177C—05/23/07
1.8V Low-Power Wide-Range Frequency Clock Driver
Pin Configuration
40-Pin MLF
Recommended Application:
DDR2 Memory Modules / Zero Delay Board Fan Out
Provides complete DDR2 DIMM logic solution
Product Description/Features:
Low skew, low jitter PLL clock driver
1 to 10 differential clock distribution (SSTL_18)
Feedback pins for input to output synchronization
Spread Spectrum tolerant inputs
Auto PD when input signal is at a certain logic state
Switching Characteristics:
Period jitter: 40ps (DDR2-400/533)
30ps (DDR2-667/800)
Half-period jitter: 60ps (DDR2-400/533)
50ps (DDR2-667/800)
OUTPUT - OUTPUT skew: 40ps (DDR2-400/533)
30ps (DDR2-667/800)
CYCLE - CYCLE jitter 40ps
52-Ball BGA
Top View
Block Diagram
ADVANCE INFORMATION
documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals.
ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners.
FBOUTT
FBOUTC
FBIN_INT
FBIN_INC
PLL
CLK_INT
CLK_INC
POWER
DOWN
AND
TEST
MODE
LOGIC
LD
AV
DD
OE
OS
LD or OE
LD, OS, or OE
PLL BYPASS
10K
Ω
- 100K
Ω
CLKT0
CLKC0
CLKT1
CLKC1
CLKT2
CLKC2
CLKT3
CLKC3
CLKT4
CLKC4
CLKT5
CLKC5
CLKT6
CLKC6
CLKT7
CLKC7
CLKT8
CLKC8
CLKT9
CLKC9
(1)
NOTE:
1. The Logic Detect (LD) powers down the device
when a logic LOW is applied to both CLK_INT and
CLK_INC.
B
C
D
E
F
G
H
J
K
A
1
2
3
4
5
6
V
D
4
3
3
3
3
3
3
3
3
3
V
D
1
1
1
1
1
1
1
1
1
2
V
D
V
D
V
DDQ
FB_INT
FB_INC
FBOUTC
30
29
28
27
26
25
24
23
22
21
FBOUTT
OE
OS
V
DDQ
GND
V
DDQ
AGND
AV
DD
CLK_INT
CLK_INC
V
DDQ
2
3
4
5
6
7
8
1
9
10
V
DDQ
CLKC2
CLKT2
CLKC7
CLKT7
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
1
2
3
4
5
6
A
B
C
D
E
F
G
H
J
K
CLKT1
CLKC1
CLKC2
CLKT2
CLK_INT
CLK_INC
AGND
AVDD
CLKT3
CLKC3
CLKT0
GND
GND
VDDQ
VDDQ
VDDQ
VDDQ
GND
GND
CLKC4
CLKC0
GND
NB
VDDQ
NB
NB
VDDQ
NB
GND
CLKT4
CLKC5
GND
NB
VDDQ
NB
NB
VDDQ
NB
GND
CLKT9
CLKT5
GND
GND
OS
VDDQ
OE
VDDQ
GND
GND
CLKC9
CLKT6
CLKC6
CLKC7
CLKT7
FB_INT
FB_INC
FB_OUTC
FB_OUTT
CLKT8
CLKC8
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