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參數(shù)資料
| 型號： | CS82C54-10Z96 |
| 廠商： | Intersil |
| 文件頁數(shù)： | 7/22頁 |
| 文件大小： | 0K |
| 描述： | IC OSC PROG TIMER 10MHZ 28PLCC |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 可編程計(jì)時(shí)器 |
| 頻率： | 10MHz |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 電流 - 電源： | 10mA |
| 工作溫度： | 0°C ~ 70°C |
| 封裝/外殼： | 28-LCC（J 形引線） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 供應(yīng)商設(shè)備封裝： | 28-PLCC（11.51x11.51） |
| 安裝類型： | 表面貼裝 |
| 產(chǎn)品目錄頁面： | 1236 (CN2011-ZH PDF) |
| 其它名稱： | CS82C54-10Z96DKR |
15
Counter will be loaded with new count on the next CLK pulse
and counting will continue from there.
Operation Common To All Modes
Programming
When a Control Word is written to a Counter, all Control
Logic, is immediately reset and OUT goes to a known initial
state; no CLK pulses are required for this.
Gate
The GATE input is always sampled on the rising edge of
CLK. In Modes 0, 2, 3 and 4 the GATE input is level
sensitive, and logic level is sampled on the rising edge of
CLK. In modes 1, 2, 3 and 5 the GATE input is rising-edge
sensitive. In these Modes, a rising edge of Gate (trigger)
sets an edge-sensitive flip-flop in the Counter. This flip-flop
is then sampled on the next rising edge of CLK. The flip-flop
is reset immediately after it is sampled. In this way, a trigger
will be detected no matter when it occurs - a high logic level
does not have to be maintained until the next rising edge of
CLK. Note that in Modes 2 and 3, the GATE input is both
edge-and level-sensitive.
Counter
New counts are loaded and Counters are decremented on
the falling edge of CLK.
The largest possible initial count is 0; this is equivalent to 216
for binary counting and 104 for BCD counting.
The counter does not stop when it reaches zero. In Modes 0,
1, 4, and 5 the Counter “wraps around” to the highest count,
either FFFF hex for binary counting or 9999 for BCD
counting, and continues counting. Modes 2 and 3 are
periodic; the Counter reloads itself with the initial count and
continues counting from there.
N
NNN
0
3
0
2
0
1
0
FF
0
3
WR
CLK
GATE
OUT
CW = 1A LSB = 3
NN
N
0
3
0
2
0
3
0
2
0
1
N
NNN
0
3
0
2
0
1
0
FF
FE
WR
CLK
GATE
OUT
CW = 1A LSB = 3
WR
CLK
GATE
OUT
CW = 1A LSB = 3
N
NN
0
FF
LSB = 5
N
0
5
0
4
FIGURE 14. MODE 5
SIGNAL
STATUS
MODES
LOW OR
GOING LOW
RISING
HIGH
0
Disables Counting
-
Enables Counting
1
-
1) Initiates
Counting
2) Resets output
after next clock
-
2
1) Disables
counting
2) Sets output
immediately high
Initiates Counting Enables Counting
3
1) Disables
counting
2) Sets output
immediately high
Initiates Counting Enables Counting
4
1) Disables
Counting
-
Enables Counting
5
-
Initiates Counting
-
FIGURE 15. GATE PIN OPERATIONS SUMMARY
MODE
MIN COUNT
MAX COUNT
010
110
220
320
410
510
NOTE: 0 is equivalent to 216 for binary counting and 104 for BCD
counting.
FIGURE 16. MINIMUM AND MAXIMUM INITIAL COUNTS
82C54
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