- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄11818 > CS82C50A-5Z96 (Intersil)IC ASYNC COMM ELEMNT UART 44PLCC PDF資料下載
參數(shù)資料
| 型號(hào)： | CS82C50A-5Z96 |
| 廠商： | Intersil |
| 文件頁(yè)數(shù)： | 4/25頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC ASYNC COMM ELEMNT UART 44PLCC |
| 標(biāo)準(zhǔn)包裝： | 500 |
| 特點(diǎn)： | 單芯片 UART/BRG |
| 通道數(shù)： | 1，UART |
| 規(guī)程： | RS232C |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 帶并行端口： | 是 |
| 帶故障啟動(dòng)位檢測(cè)功能： | 是 |
| 帶調(diào)制解調(diào)器控制功能： | 是 |
| 帶CMOS： | 是 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 44-PLCC |
| 包裝： | 帶卷 (TR) |
第1頁(yè)第2頁(yè)第3頁(yè)當(dāng)前第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)
12
FN2958.5
August 24, 2006
data in the RBR before complete reception of the next
character result in the loss of the data in the Receiver
Register. The OE flag in the LSR register indicates the
overrun condition.
TRANSMITTER HOLDING REGISTER (THR)
The Transmitter Holding Register (THR) holds parallel data
from the data bus (D0-D7) until the Transmitter Shift Register
is empty and ready to accept a new character for
transmission. The transmitter and receiver word length and
number of stop bits are the same. If the character is less
than eight bits, unused bits at the microprocessor data bus
are ignored by the transmitter.
Data Bit 0 (THR(0)) is the first serial data bit transmitted. The
THRE flag (LSR(5)) reflect the status of the THR. The TEMT
flag (LSR(6)) indicates if both the THR and TSR are empty.
SCRATCHPAD REGISTER (SCR)
This 8-bit Read/Write register has no effect on the 82C50A.
It is intended as a scratchpad register to be used by the
programmer to hold data temporarily.
Interrupt Structure
INTERRUPT IDENTIFICATION REGISTER (IIR)
The 82C50A has interrupt capability for interfacing to current
microprocessors. In order to minimize software overhead
during data character transfers, the 82C50A prioritizes
interrupts into four levels. The four levels of interrupt
conditions are as follows:
1. Receiver Line Status (Priority 1)
2. Received Data Ready (Priority 2)
3. Transmitter Holding Register Empty (Priority 3)
4. Modem Status (Priority 4).
Information indicating that a prioritized interrupt is pending
and the type of interrupt is stored in the Interrupt
Identification Register (IIR). When addressed during chip
select time, the lIR indicates the highest priority interrupt
pending. No other interrupts are acknowledged until the
interrupt is serviced by the CPU. The contents of the lIR are
indicated in Table 2 and are described below.
IIR(0): IIR(0) can be used in either a hardwired prioritized or
polled environment to indicate whether an interrupt is
pending. When IIR(0) is low, an interrupt is pending, and the
lIR contents may be used as a pointer to the appropriate
interrupt service routine. When lIR(0) is high, no interrupt is
pending.
IlR(1) and IIR(2): llR(1) and IlR(2) are used to identify the
highest priority interrupt pending as indicated in Table 2.
lIR(3) - IIR(7): These five bits of the lIR are logic 0.
RBR Bits 0 thru 7
RBR (0)
Data Bit 0
RBR (1)
Data Bit 1
RBR (2)
Data Bit 2
RBR (3)
Data Bit 3
RBR (4)
Data Bit 4
RBR (5)
Data Bit 5
RBR (6)
Data Bit 6
RBR (7)
Data Bit 7
THR Bits 0 thru 7
THR (0)
Data Bit 0
THR (1)
Data Bit 1
THR (2)
Data Bit 2
THR (3)
Data Bit 3
THR (4)
Data Bit 4
THR (5)
Data Bit 5
THR (6)
Data Bit 6
THR (7)
Data Bit 7
SCR Bits 0 thru 7
SCR (0)
Data Bit 0
SCR (1)
Data Bit 1
SCR (2)
Data Bit 2
SCR (3)
Data Bit 3
SOR (4)
Data Bit 4
SCR (5)
Data Bit 5
SOR (6)
Data Bit 6
SCR (7)
Data Bit 7
TABLE 2. INTERRUPT IDENTIFICATION REGISTER
INTERRUPT IDENTIFICATION
INTERRUPT SET AND RESET FUNCTIONS
BIT 2
BIT 1
BIT 0
PRIORITY
LEVEL
INTERRUPT FLAG
INTERRUPT SOURCE
INTERRUPT
RESET CONTROL
X
1
None
1
0
First
Receiver Line Status
OE, PE, FE, or BI
LSR Read
1
0
Second
Received Data Available
Receiver Data Available
RBR Read
0
1
0
Third
THRE
IIR Read if THRE is the
Interrupt Source or THR Write
0
Fourth
Modem Status
CTS, DSR, RI, DCD
MSR Read
NOTE:
X = Not Defined, May Be 0 or 1
82C50A
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CS82C50A-5Z | IC COMMUNICATION ELEMENT 44-PLCC |
| CP82C52Z | IC UART/BRG 5V 16MHZ 28-PDIP |
| ATUC128D4-AUR | IC MCU 32BIT 128KB FLASH 48TQFP |
| VI-B72-IW-F2 | CONVERTER MOD DC/DC 15V 100W |
| V24C12H150B2 | CONVERTER MOD DC/DC 12V 150W |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CS82C52 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CS82C5296 | 功能描述:IC UART/BRG 5V 16MHZ 28-PLCC RoHS:否 類別:集成電路 (IC) >> 接口 - UART（通用異步接收器/發(fā)送器） 系列:- 標(biāo)準(zhǔn)包裝:250 系列:- 特點(diǎn):* 通道數(shù):2，DUART FIFO's:16 字節(jié) 規(guī)程:RS232，RS485 電源電壓:2.25 V ~ 5.5 V 帶并行端口:- 帶自動(dòng)流量控制功能:是 帶IrDA 編碼器/解碼器:是 帶故障啟動(dòng)位檢測(cè)功能:是 帶調(diào)制解調(diào)器控制功能:是 帶CMOS:是 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應(yīng)商設(shè)備封裝:48-TQFP（7x7） 包裝:托盤 其它名稱:XR16L2551IM-F-ND |
| CS82C52Z | 功能描述:UART 接口集成電路 A/ANNEAL PERIPH UART /BRG 5V 16MHZ 28PLCC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| CS82C52Z96 | 功能描述:UART 接口集成電路 A/ANNEAL PERIPH UART /BRG 5V 16MHZ 28PLCC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| CS82C54 | 功能描述:計(jì)時(shí)器和支持產(chǎn)品 PERIPH PRG-CNTR 5V 8MHZ 28PLCC COM RoHS:否 制造商:Micrel 類型:Standard 封裝 / 箱體:SOT-23 內(nèi)部定時(shí)器數(shù)量:1 電源電壓-最大:18 V 電源電壓-最小:2.7 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Reel |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。