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參數(shù)資料
| 型號： | CS61577-IP1 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | T1/E1 LINE INTERFACE |
| 中文描述： | 的T1/E1線路接口 |
| 文件頁數(shù)： | 12/44頁 |
| 文件大?。?/td> | 632K |
| 代理商： | CS61577-IP1 |
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put from the phase selector feeds the clock and
data recovery circuits which generate the recov-
ered clock and sample the incoming signal at
appropriate intervals to recover the data.
Data sampling will continue at the periods se-
lected by the phase selector until an incoming
pulse deviates enough to cause a new phase to be
selected for data sampling. The phases of the de-
lay line are selected and updated to allow as much
as 0.4 UI of jitter from 10 kHz to 100 kHz, with-
out error. The jitter tolerance of the receiver
exceeds that shown in Figure 11. Additionally,
this method of clock and data recovery is tolerant
of long strings of consecutive zeros. The data
sampler will continuously sample data based on
its last input until a new pulse arrives to update
the clock phase selector.
The delay line is continuously calibrated using
the crystal oscillator reference clock. The delay
line produces 13 phases for each cycle of the ref-
erence clock. In effect, the 13 phases are
analogous to a 20 MHz clock when the reference
clock is 1.544 MHz. This implementation utilizes
the benefits of a 20 MHz clock for clock recovery
without actually having the clock present to im-
pede analog circuit performance.
In the Hardware Mode, data at RPOS and RNEG
should be sampled on the rising edge of RCLK,
the recovered clock. In the Extended Hardware
Mode, data at RDATA should be sampled on the
falling edge of RCLK. In the Host Mode, CLKE
determines the clock polarity for which output
data should be sampled as shown in Table 5.
10
1k
10k
1
100
100k
700
.1
1
10
100
.4
28
300
138
300
PEAK-TO-PEAK
JITTER
(unit intervals)
JITTER FREQUENCY (Hz)
AT&T 62411
Minimum
Performance
Figure 11. Minimum Input Jitter Tolerance of Receiver
(Clock Recovery Circuit and Jitter Attenuator)
1 : 2
RTIP
RRING
RPOS
RNEG
RCLK
Data
Level
Slicer
Data
Sampling
& Clock
Extraction
Jitter
Attenuator
Edge
Detector
Clock
Phase
Selector
Continuously
Calibrated
Delay Line
Figure 10. Receiver Block Diagram
CS61577
12
DS155PP2
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CS61577-IP1 | T1/E1 LINE INTERFACE |
| CS61577-IL1 | T1/E1 LINE INTERFACE |
| CS61577 | T1/E1 Line Interface(T1/E1線接口) |
| CS8 | Phase Control Thyristors |
| CS8-08IO2 | Phase Control Thyristors |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CS6157AT | 制造商:Rochester Electronics LLC 功能描述:- Tape and Reel |
| CS6158 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| CS61581 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:T1/E1 Universal Line Interface |
| CS61581-IL | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:T1/E1 Universal Line Interface |
| CS61581ILZ | 制造商:CIRRUS 功能描述:Pb Free |
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