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參數(shù)資料
| 型號： | CS5565-ISZ |
| 廠商： | Cirrus Logic Inc |
| 文件頁數(shù)： | 1/4頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC DELTA-SIGMA 24BIT 24-SSOP |
| 標(biāo)準(zhǔn)包裝： | 59 |
| 位數(shù)： | 24 |
| 數(shù)據(jù)接口： | 串行，并聯(lián) |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-SSOP（0.209"，5.30mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 24-SSOP |
| 包裝： | 管件 |
| 其它名稱： | 598-1268-5 |
Copyright
Cirrus Logic, Inc. 2007
(All Rights Reserved)
CS556x / 7x / 8x:
Converting Output Data from Serial to Parallel
1. Introduction
The CS556X, CS557X, and CS558X series of high-throughput Delta-Sigma A/D converters output data in serial for-
mat. Some applications may require that data be available in parallel format. This application note will discuss how
to use common serial-to-parallel register ICs to provide parallel data output capability for these A/D converters.
Some A/D converters provide parallel output data as an output option. While this makes for faster data transfer it
can introduce some possible compromises in the performance of the A/D converter. A parallel interface requires
many more pins on the A/D than a serial interface. This factor can increase the cost, but a larger concern should
be how a parallel interface can reduce performance. The data interface has many more connections via bond wires
to the semiconductor die. When the digital data on the digital bus is changing each bond wire acts as a radiator of
an electromagnetic field. This electromagnetic field can interfere with the performance of the converter. The digital
activity on the bus need not be due to the converter itself but may be caused by other peripherals using the same
bus. Many A/D converters that have parallel interfaces recommend that bus activity be stopped when a conversion
is performed, and that the data from the converter be read when the converter is not performing a conversion. An-
other option would be to provide a second set of latches outside the A/D to isolate the bus activity from being on the
digital output pins of the converter itself.
2. The CS556x/7x/8x
Cirrus Logic has chosen to offer the CS556X/7X/8X series of converters with only a serial interface. This reduces
the package pin count and also reduces the number of digital interface pins that can radiate noise onto the converter
die. The serial interface provides two different modes of operation. The serial port on the converter can operate in
either master mode, where the converter itself outputs the data according to its own timing (this mode is called the
SSC mode, synchronous self-clock mode). The second mode is where the serial port acts as a slave device to an
external controller, where the serial data is output from the port according to the clock provided by the external de-
vice (this mode is the SEC mode, synchronous external clock mode).
3. Serial-to-Parallel Conversion
If an application requires a parallel interface to read the converter data, then the A/D can be configured in the SSC
serial port mode and directly interfaced to serial-to-parallel registers. Figure 1 illustrates the CS556x/7x/8x A/D con-
verter interfaced to a set of 74VHC595 serial-to-parallel registers. The SMODE pin of the converter is tied to the
VL supply (tied high) to set the serial port mode of the converter into the SSC (master) mode. At the end of each
conversion the RDY output from the converter will transition low, and the SCLK and the SDO outputs will become
active. The data bits from SDO will be shifted into the first 74VHC595 register by the rising edges of SCLK. The
74VHC595 device holds eight bits of data. Multiple 74HVC595 devices are daisy-chained to provide either a 16-
bit parallel (two 74VHC595s) or a 24-bit parallel (three 74VHC595s) interface. The 74VHC595 has a tri-state output
so the outputs of these devices can be attached to a multi-peripheral bus. The RDY signal will return high when all
the bits from the converter have been shifted into the registers. When RDY transitions high it will set the NC75Z175
latch to provide a "data ready" signal at its Q output. When the read signal from the system goes low, the outputs
of the 74VHC595 devices will come out of tri-state and place their data on the bus. The falling read signal will also
clear the "data ready" signal back to a zero at the Q output of the NC75Z175 latch.
AN313
JUN
‘07
AN311REV1
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CS5565-ISZR | 制造商:Cirrus Logic 功能描述: |
| CS5566 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:±2.5 V / 5 V, 5 kSps, 24-bit ΔΣ ADC |
| CS5566_09 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:±2.5 V / 5 V, 5 kSps, 24-bit ΔΣ ADC |
| CS5566-ISZ | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 24-Bit 5 kSps ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| CS5566-ISZR | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC IC ADC DELTA-SIGMA 24-SSOP 24b/5kSPS RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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