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參數(shù)資料
| 型號： | CS5534-BSZ |
| 廠商： | Cirrus Logic Inc |
| 文件頁數(shù)： | 18/43頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 24BIT 4CH W/LNA 24SSOP |
| 標準包裝： | 59 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 3.84k |
| 數(shù)據(jù)接口： | 串行 |
| 轉換器數(shù)目： | 1 |
| 功率耗散（最大）： | 45mW |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-SSOP（0.209"，5.30mm 寬） |
| 供應商設備封裝： | 24-SSOP |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 4 個差分，單極；4 個差分，雙極 |
| 產(chǎn)品目錄頁面： | 755 (CN2011-ZH PDF) |
| 配用： | 598-1016-ND - EVAL BOARD FOR CS5534 |
| 其它名稱： | 598-1116-5 |
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CS5531/32/33/34-AS
DS289F5
25
from VA+ and VA-. Their output voltage will be
limited to the VA+ voltage for a logic 1 and VA-
for a logic 0.
2.3.7. Offset and Gain Select
The Offset and Gain Select bit (OGS) is used to se-
lect the source of the calibration registers to use
when performing conversions and calibrations.
When the OGS bit is set to ‘0’, the offset and gain
registers corresponding to the desired physical
channel (CS1-CS0 in the selected Setup) will be ac-
cessed. When the OGS bit is set to ‘1’, the offset
and gain registers pointed to by the OG1-OG0 bits
in the selected Setup will be accessed. This feature
allows multiple calibration values (e.g. for different
gain settings) to be used on a single physical chan-
nel without having to re-calibrate or manipulate the
calibration registers.
2.3.8. Filter Rate Select
The Filter Rate Select bit (FRS) modifies the output
word rates of the converter to allow either 50 Hz or
60 Hz
rejection
when
operating
from
a
4.9152 MHz crystal. If FRS is cleared to logic 0,
the word rates and corresponding filter characteris-
tics can be selected (using the Channel Setup Reg-
isters) from 7.5, 15, 30, 60, 120, 240, 480, 960,
1920, or 3840 Sps when using a 4.9152 MHz clock.
If FRS is set to logic 1, the word rates and corre-
sponding filter characteristics scale by a factor of
5/6, making the selectable word rates 6.25, 12.5,
25, 50, 100, 200, 400, 800, 1600, and 3200 Sps
when using a 4.9152 MHz clock. When using other
clock frequencies, these selectable word rates will
scale linearly with the clock frequency that is used.
VREF
C= 14pF
f=
2
φ Fine
1
V
≤ 8mV
i= fV
C
os
n
φ Coarse
MCLK
16
VRS = 1; 1 V
≤ V
≤ 2.5 V
REF
Figure 9. Input Reference Model when VRS = 1
VREF
C= 7 pF
f=
2
φ Fine
1
V
≤ 16 mV
i= fV
C
os
n
φ Coarse
MCLK
16
VRS = 0; 2.5 V < V
≤ VA+
REF
Figure 10. Input Reference Model when VRS = 0
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CS5534-BSZ/H | 制造商:Cirrus Logic 功能描述: |
| CS5534-BSZR | 功能描述:模數(shù)轉換器 - ADC IC 24-Bit ADCs w/UltraLw Noise PGIA RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| CS5535 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CS5535-UDC | 制造商:Advanced Micro Devices 功能描述:Companion Device 208-Pin BGA 制造商:Rochester Electronics LLC 功能描述:I/O COMPANION - Bulk |
| CS5536AC B1 | 制造商:Advanced Micro Devices 功能描述:Companion Device 208-Pin BGA 制造商:Advanced Micro Devices 功能描述:GEO IC OPN - Trays |
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