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參數(shù)資料
| 型號(hào)： | CS5368-CQZ |
| 廠商： | Cirrus Logic Inc |
| 文件頁數(shù)： | 17/19頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 8CH 114DB 216KHZ 48-LQFP |
| 標(biāo)準(zhǔn)包裝： | 250 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 216k |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 1.12W |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-LQFP（7x7） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 8 個(gè)差分，單極 |
| 產(chǎn)品目錄頁面： | 755 (CN2011-ZH PDF) |
| 配用： | 598-1157-ND - BOARD EVAL FOR CS5368 192KHZ ADC |
| 其它名稱： | 598-1090 |
DS624F4
7
CS5368
Pin Name
Pin #
Pin Description
AIN2+, AIN2-
AIN4+, AIN4-
AIN3+, AIN3-
AIN7+, AIN7-
AIN8+, AIN8-
AIN6+, AIN6-
AIN5+, AIN5-
AIN1+, AIN1-
1,2
11,12
13,14
15,16
17,18
43,44
45,46
47,48
Differential Analog (Inputs) - Audio signals are presented differently to the delta sigma modula-
tors via the AIN+/- pins.
GND
3,8
10,19
29,32
Ground (Input) - Ground reference. Must be connected to analog ground.
VA
4,9
Analog Power (Input) - Positive power supply for the analog section
REF_GND
5
Reference Ground (Input) - For the internal sampling circuits. Must be connected to analog
ground.
FILT+
6
Positive Voltage Reference (Output) - Reference voltage for internal sampling circuits.
VQ
7
Quiescent Voltage (Output) - Filter connection for the internal quiescent reference voltage.
VX
20
Crystal Oscillator Power (Input) - Also powers control logic to enable or disable oscillator cir-
cuits.
XTI
XTO
21
22
Crystal Oscillator Connections (Input/Output) - I/O pins for an external crystal which may be
used to generate MCLK.
MCLK
23
System Master Clock (Input/Output) - When a crystal is used, this pin acts as a buffered MCLK
Source (Output). When the oscillator function is not used, this pin acts as an input for the system
master clock. In this case, the XTI and XTO pins must be tied low.
LRCK/FS
24
Serial Audio Channel Clock (Input/Output)
In IS Mode, Serial Audio Channel Select. When low, the odd channels are selected.
In LJ Mode, Serial Audio Channel Select. When high, the odd channels are selected.
In TDM Mode, a frame sync signal. When high, it marks the beginning of a new frame of serial
audio samples. In Slave Mode, this pin acts as an input pin.
SCLK
25
Main timing clock for the Serial Audio Interface (Input/Output) - During Master Mode, this pin
acts as an output, and during Slave Mode it acts as an input pin.
SDOUT4
26
Serial Audio Data (Output) - Channels 7,8.
SDOUT2
27
Serial Audio Data (Output) - Channels 3,4.
VLS
28
Serial Audio Interface Power (Input) - Positive power for the serial audio interface.
SDOUT1/TDM
30
Serial Audio Data (Output) - Channels 1,2.
SDOUT3/TDM
31
Serial Audio Data (Output) - Channels 5,6. TDM is complementary TDM data.
VD
33
Digital Power (Input) - Positive power supply for the digital section.
VLC
35
Control Port Interface Power(Input) - Positive power for the control port interface.
OVFL
36
Overflow (Output, open drain) - Detects an overflow condition on both left and right channels.
RST
41
Reset (Input) - The device enters a low power mode when low.
Stand-Alone Mode
CLKMODE
34
CLKMODE (Input) - Setting this pin HIGH places a divide-by-1.5 circuit in the MCLK path to the
core device circuitry.
DIF1
DIF0
37
38
DIF1, DIF0 (Input) - Inputs of the audio interface format.
M1
M0
39
40
Mode Selection (Input) - Determines the operational mode of the device.
MDIV
42
MCLK Divider (Input) - Setting this pin HIGH places a divide-by-2 circuit in the MCLK path to the
core device circuitry.
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