參數(shù)資料
型號: CS5364-DQZ
廠商: Cirrus Logic Inc
文件頁數(shù): 17/42頁
文件大小: 0K
描述: IC ADC 4CH 114DB 216KHZ 48-LQFP
標準包裝: 250
位數(shù): 24
采樣率(每秒): 216k
數(shù)據(jù)接口: 串行
轉換器數(shù)目: 1
功率耗散(最大): 580mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 105°C
安裝類型: 表面貼裝
封裝/外殼: 48-LQFP
供應商設備封裝: 48-LQFP(7x7)
包裝: 管件
輸入數(shù)目和類型: 4 個差分,單極
產(chǎn)品目錄頁面: 755 (CN2011-ZH PDF)
配用: CDB5364-ND - EVALUATION BOARD FOR CS5364
其它名稱: 598-1697
24
DS625F4
CS5364
4.6.3
Master Mode Clock Dividers
Figure 13 shows the configuration of the MCLK dividers and the sample rate dividers for Master Mode, in-
cluding the significance of each MCLK divider pin (in Stand-Alone Mode) or bit (in Control Port Mode).
Figure 13. Master Mode Clock Dividers
4.6.4
Slave Mode Audio Clocking With Auto-Detect
In Slave Mode, CS5364 auto-detects speed mode, which eliminates the need to configure M1 and M0 when
changing among speed modes. The external MCLK is subject to clock dividers as set by the clock divider
pins in Stand-Alone Mode or the clock divider bits in Control Port Mode. The CS5364 compares the divided-
down, internal MCLK to the incoming LRCK/FS and sets the speed mode based on the MCLK/LRCK ratio
as shown in Figure 14.
Figure 14. Slave Mode Auto-Detect Speed
÷128
÷ 64
M0
M1
LRCK/ FS
Single
Speed
Quad
Speed
Double
Speed
00
01
10
÷ 2
÷ 4
÷ 1
SCLK
Single
Speed
Quad
Speed
Double
Speed
00
01
10
÷ 256
pin
CLKMODE
MDIV
n/a
MCLK
÷ 1
÷ 1.5
÷ 2
÷ 1
÷ 2
÷ 1
bit
MDIV1
MDIV0
0/1
MCLK DIVIDERS
SAMPLE RATE DIVIDERS
CLKMODE
128
64
Single-Speed
256
pin
CLKMODE
MDIV
n/a
External
MCLK
÷ 1
÷ 1.5
÷ 2
÷ 1
÷ 2
÷ 1
bit
MDIV1
MDIV0
0/1
MCLK DIVIDERS
CLKMODE
÷LRCK
LRCK
Double-Speed
Quad-Speed
SPEED MODE
Internal
MCLK
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