參數(shù)資料
型號： CS5361GD16
英文描述： Analog IC
中文描述： 模擬IC
文件頁數(shù)： 1/16頁
文件大?。?/td> 116K
代理商： CS5361GD16
Semiconductor Components Industries, LLC, 2001
October, 2001 – Rev. 10
1
Publication Order Number:
CS5361/D
CS5361
Battery Charger
Buck Controller
The CS5361 is a high voltage step down controller that provides a
simple way to build a battery charger suited for various types of
batteries. With an operating range of up to 30 V, it can be used to
charge a multiple number of cells from a DC voltage, as is supplied by
high AC–DC adapter voltages. Proprietary I
2
architecture ensures full
control over both Average and Peak charging currents. Independent
voltage loop allows for precision regulation of the battery voltage.
Average current outer control loop provides tight regulation and easy
loop compensation while pulse by pulse inner control provides for fast
response.
The CS5361 is designed to provide a high performance,
full–featured battery charger that is simple to use. A 4.2 V reference
with 0.8% tolerance can be used to implement 1.0% accurate output
voltages. It also features an additional pulse–by–pulse current limit
input to allow for fast output current control.
The CS5361 operates over a 7.0 V to 30 V range and is available in a
16 lead surface mount narrow body.
Features
Switching Regulator Controller
–
Synchronous Buck Regulator Topology for High Efficiency
–
Top Side P–Channel Allows High Input Voltage and
Requires No Charge Pump
–
Pulse–by–Pulse Inner Control Loop for Fast Response
–
Programmable Peak Current Limit
–
True Current Soft Start
–
Clamped Gate–to–Source Voltage
Oscillator
–
Constant Frequency Design
–
100 kHz to 500 kHz Adjustable Frequency
System Power Management
–
Programmable UVLO
–
2.0
μ
A Sleep Mode Current (Typical)
–
Bias Mode Uses Top Switch to Connect Battery to Load
–
4.2 V
±
0.8% Reference Output
–
Thermal Shutdown
http://onsemi.com
Device
Package
Shipping
ORDERING INFORMATION
CS5361GD16
SO–16
48 Units/Rail
CS5361GDR16
SO–16
2500 Tape & Reel
SO–16
D SUFFIX
CASE 751B
V
FB
V
COMP
1
5
Y
16
I
PEAK
I
AVG
IS–
V
REF
IS+
I
COMP
PGND
LGND
GATE(L)
V
REF(IN)
V
CC
OSC
GATE(H)
ENABLE/UVLO
PIN CONNECTIONS AND
MARKING DIAGRAM
1
16
A
YY, Y
WW, W = Work Week
= Assembly Location
= Year
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