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參數(shù)資料
| 型號： | CS5303GDW28 |
| 英文描述： | Analog IC |
| 中文描述： | 模擬IC |
| 文件頁數(shù)： | 5/20頁 |
| 文件大?。?/td> | 176K |
| 代理商： | CS5303GDW28 |
CS5303
http://onsemi.com
5
ELECTRICAL CHARACTERISTICS (continued)
(0
°
C < T
A
< 70
°
C; 0
°
C < T
J
< 125
°
C; 4.7
V < V
CCL
< 14
V; 8
V < V
CCH
< 20
V;
C
GATE(H)
= 3.3
nF, C
GATE(L)
= 3.3
nF, R
R(OSC)
= 53.6
k, C
COMP
= 0.1
μ
F, C
REF
= 0.1
μ
F, DAC Code 10000, C
VCC
= 1.0
μ
F, I
LIM
≥
1
V;unless other-
wise specified)
Characteristic
Test Conditions
Min
Typ
Max
Unit
PWM Comparators
Minimum Pulse Width
Measured from CSx to GATE(H)
V(V
FB
) = V(CS
REF
) = 1.0 V, V(COMP) = 1.5 V
60
mV step applied between V
CSX
and V
CREF
–
350
515
ns
Channel Start Up Offset
V(CS1) = V(CS2) = V(CS3) = V(V
FB
) = 0.3
V(CS
REF
) = 0
V; Measure V(COMP) when
GATE1(H), 2(H), 3(H) switch high
0.4
0.5
–
V
Gate(H) and Gate(L)
High Voltage (AC)
Note 4. Measure V
CCLX
– Gate(L) or
V
CCHX
– Gate(H)
–
0
1.0
V
Low Voltage (AC)
Note 4., Measure Gate(L) or Gate(H)
–
0
0.5
V
Rise Time Gate(H)x
1.0 V < GATE < 8.0 V; V
CCHX
= 10 V
–
35
80
ns
Rise Time Gate(L)x
1.0 V < GATE < 8.0 V; V
CCLX
= 10 V
–
35
80
ns
Fall Time Gate(H)x
8.0 V > GATE > 1.0 V; V
CCHX
= 10 V
–
35
80
ns
Fall Time Gate(L)
8.0 V > GATE > 1.0 V; V
CCLX
= 10 V
–
35
80
ns
Gate(H) to Gate(L) Delay
Gate(H) < 2.0 V, Gate(L) > 2 V
30
65
110
ns
Gate(L) to Gate(H) Delay
Gate(L) < 2.0 V, Gate(H) > 2 V
30
65
110
ns
GATE Pull–down
Force 100
μ
A into Gate Driver with no power
applied to V
CCHX
and V
CCLX
= 2 V.
–
1.2
1.6
V
Oscillator
Switching Frequency
Measure any phase (R
OSC
= 53.6 k)
220
250
280
kHz
Switching Frequency
Note 4. Measure any phase (R
OSC
= 32.4 k)
300
400
500
kHz
Switching Frequency
Note 4. Measure any phase (R
OSC
= 16.2 k)
600
800
1000
kHz
R
OSC
Voltage
–
–
1.00
–
V
Phase Delay
–
105
120
135
deg
Adaptive Voltage Positioning
V
DRP
Output Voltage to DAC
OUT
Offset
CS1 = CS2 = CS3 = CS
REF
, V
FB
= COMP
Measure V
DRP
– COMP
–20
–
20
mV
Maximum V
DRP
Voltage
|(CS1 = CS2 = CS3) – C
REF
| = 50 mV,
V
FB
= COMP, Measure V
DRP
– COMP
360
465
570
mV
Current Sense Amp to V
DRP
Gain
–
2.4
3.0
3.8
V/V
Current Sensing and Sharing
CS1–CS3 Input Bias Current
V(CSx) = V(CS
REF
) = 0 V
–
0.2
2.0
μ
A
CS
REF
Input Bias Current
–
–
0.6
6.0
μ
A
Current Sense Amplifiers Gain
–
3.8
4.3
4.8
V/V
Current Sense Amp Mismatch
(The sum of offset and gain errors)
Note 4. 0
≤
(CSx – CS
REF
)
≤
50 mV
–5.0
–
5.0
mV
Current Sense Amplifiers Input
Common Mode Range Limit
Note 4. 7 V < V
CCLL1
< 12 V
0
–
V
CCLL1
– 2
V
Current Sense Input to I
LIM
Gain
0.25 V < I
LIM
< 1.20 V
5.0
6.5
8.0
V/V
Current Limit Filter Slew Rate
Note 4.
7.5
15.0
40.0
mV/
μ
s
4. Guaranteed by design. Not tested in production.
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相關代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CS5303GDWR28 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
| CS5305 | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:Three−Phase Synchronous Switching Step−Down Controller with Single Wire Current Sharing |
| CS5305/D | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Three-Phase Synchronous Switching Step-Down Controller with Single Wire Current Sharing |
| CS5305GDW28 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:ON Semiconductor 功能描述: |
| CS5305GDWR28 | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:Three−Phase Synchronous Switching Step−Down Controller with Single Wire Current Sharing |
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