參數(shù)資料
型號: CS4361-CZZ
廠商: Cirrus Logic Inc
文件頁數(shù): 6/24頁
文件大小: 0K
描述: IC DAC STER 6CH 103DB 20TSSOP
標(biāo)準(zhǔn)包裝: 74
位數(shù): 24
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 6
電壓電源: 單電源
功率耗散(最大): 455mW
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 20-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 20-TSSOP
包裝: 管件
輸出數(shù)目和類型: 6 電壓,單極
采樣率(每秒): 192k
產(chǎn)品目錄頁面: 757 (CN2011-ZH PDF)
配用: 598-1153-ND - BOARD EVAL FOR CS4361
其它名稱: 598-1057-5
14
CS4361
Confidential Draft
9/30/11
4.3
De-Emphasis
The CS4361 includes on-chip digital de-emphasis. Figure 11 shows the de-emphasis curve for Fs equal to
44.1 kHz. The frequency response of the de-emphasis curve will scale proportionally with changes in sam-
ple rate, Fs. The de-emphasis filter is active (inactive) if the DEM/SCLK pin is low (high) for five consecutive
falling edges of LRCK. This function is available only in the internal Serial Clock Mode when LRCK < 50 kHz.
4.4
Mode Select
Mode selection is determined by the Mode Select pin. The value of this pin is locked 1024 LRCK cycles after
RST is released. This pin requires a specific connection to supply, ground, MCLK, or LRCK as outlined in
Table 2. Mode Pin Settings
Mode pin is:
Mode
Figure
Tied to VL
IS
Tied to GND
Left-Justified
Tied to LRCK
Right-Justified - 24 bit
Tied to MCLK
Right-Justified - 16bit
LRCK
SCLK
Left Channel
Right Channel
SDATA
654321
0
98
7
15 14 13 12 11 10
6543
210
98
7
15 14 13 12 11 10
32 clocks
Internal SCLK Mode
External SCLK Mode
Right-Justified, 16-Bit Data
INT SCLK = 32 Fs if
MCLK/LRCK = 1024, 512, 256, 128, or 64
INT SCLK = 48 Fs if
MCLK/LRCK = 768, 384, 192, or 96
INT SCLK = 72 Fs if
MCLK/LRCK = 1152
Right-Justified, 16-Bit Data
Data Valid on Rising Edge of SCLK
SCLK Must Have at Least 32 Cycles per LRCK Period
Figure 10. CS4361 Data Format (Right-Justified 16)
Gain
dB
-10dB
0dB
Frequency
T2 = 15 s
T1=50 s
F1
F2
3.183 kHz
10.61 kHz
Figure 11. De-Emphasis Curve (Fs = 44.1kHz)
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