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參數(shù)資料
| 型號： | CS4352-DZZR |
| 廠商： | Cirrus Logic Inc |
| 文件頁數(shù)： | 5/20頁 |
| 文件大小： | 0K |
| 描述： | IC DAC STER 102DB 192KHZ 20TSSOP |
| 標(biāo)準(zhǔn)包裝： | 4,000 |
| 位數(shù)： | 24 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 模擬和數(shù)字 |
| 功率耗散（最大）： | 158mW |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-TSSOP |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 2 電壓，單極 |
| 采樣率（每秒）： | 192k |
| 配用： | 598-1518-ND - BOARD EVAL FOR CS4352 DAC |
DS684F2
13
CS4352
4.4
De-Emphasis Control
The device includes on-chip digital de-emphasis. Figure 6 shows the de-emphasis curve for Fs equal to
44.1 kHz. The frequency response of the de-emphasis curve scales with changes in sample rate, Fs. The
De-emphasis error will increase for sample rates other than 44.1 kHz
When pulled to VL, the DEM pin activates the 44.1 kHz de-emphasis filter. When pulled to GND, the DEM
pin turns off the de-emphasis filter.
Note:
De-emphasis is only available in Single-Speed Mode.
4.5
Recommended Power-Up Sequence
1.
Hold RST low until the power supplies and configuration pins are stable, and the master and left/right
clocks are locked to the appropriate frequencies, as discussed in Section 4.2. In this state, VQ will re-
main low and VBIAS will be connected to VA.
2.
Bring RST high. The device will remain in a low power state with VQ low and will initiate the power-up
sequence after approximately 512 LRCK cycles in Single-Speed Mode (1024 LRCK cycles in Double-
Speed Mode, and 2048 LRCK cycles in Quad-Speed Mode).
4.6
Grounding and Power Supply Arrangements
As with any high-resolution converter, the CS4352 requires careful attention to power supply and grounding
arrangements if its potential performance is to be realized. Figure 2 shows the recommended power ar-
rangements, with VA_H, VA, VD, and VL connected to clean supplies. If the ground planes are split between
digital ground and analog ground, the GND pins of the CS4352 should be connected to the analog ground
plane.
All signals, especially clocks, should be kept away from the VBIAS and VQ pins in order to avoid unwanted
coupling into the DAC.
4.6.1
Capacitor Placement
Decoupling capacitors should be placed as close to the DAC as possible, with the low-value ceramic ca-
pacitor being the closest. To further minimize impedance, these capacitors should be located on the same
layer as the DAC. If desired, all supply pins may be connected to the same supply, but a decoupling ca-
pacitor should still be placed on each supply pin.
Note:
All decoupling capacitors should be referenced to analog ground.
The CDB4352 evaluation board demonstrates the optimum layout and power supply arrangements.
Gain
dB
-10dB
0dB
Frequency
T2 = 15 s
T1=50 s
F1
F2
3.183 kHz
10.61 kHz
Figure 6. De-Emphasis Curve
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| CS4353-CNZ | 功能描述:數(shù)模轉(zhuǎn)換器- DAC IC 3.3V Str DAC w/2Vrms line output RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| CS4353-CNZR | 功能描述:數(shù)模轉(zhuǎn)換器- DAC IC 3.3V Str DAC w/2Vrms line output RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
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