參數(shù)資料
型號: CS42L52-DNZR
廠商: CIRRUS LOGIC INC
元件分類: 消費家電
中文描述: SPECIALTY CONSUMER CIRCUIT, QCC40
封裝: 6 X 6 MM, LEAD FREE, MO-220, QFN-40
文件頁數(shù): 27/59頁
文件大?。?/td> 1800K
代理商: CS42L52-DNZR
DS680F1
33
CS42L52
5/13/08
4.4.2
Overriding the PGA Power Down
To accommodate automatic activation of the headphone amplifier when the SPK/HP_SW switch pin
changes, the CS42L52 will automatically power up the PGA whenever passthrough is enabled, regard-
less of the PDN_PGA setting. Refer to the table below for details on how this PGA power-down override
functions in accordance with the state of the headphone channels. The shaded cells represent normal
PGA operation when passthrough is disabled.
When passthrough is enabled, turning the headphone channel ON (by writing ‘11’b to HPx_PDN[1:0] or
by automatic activation of the headphone detect switch, SPK/HP_SW) will automatically disable the
PGAx_PDN in order to transmit the analog signal to the headphone.
4.5
PWM Outputs
4.5.1
Mono Speaker Output Configuration
The CS42L52 accommodates a stereo as well as a mono speaker output configuration. In mono mode
the output drivers of each channel are connected in parallel to deliver maximum power to a 4 ohm speak-
er. Refer to the table below for pin mapping in mono configuration.
4.5.2
VP Battery Compensation
The CS42L52 provides the option to maintain a desired power output level, independent of the VP supply.
When enabled, this feature works by monitoring the voltage on the VP supply and reducing the attenua-
tion on the speaker outputs when VP voltage levels fall.
Note:
The internal ADC that monitors the VP supply operates from the VA supply. Calculations are
based on typical VA levels of 1.8 V and 2.5 V using the VPREF bits.
Referenced Control
Register Location
PDN_ADCx .........................
PASSTHRU .........................
PDN_OVRD ........................
SPKx_PDN[1:0]...................
PDN_PGA
PASSTHRU
HP Channel
PGA Status
0
x
Powered UP
1
0
x
Powered DOWN
1
OFF
Powered DOWN
ON
Powered UP
Referenced Control
Register Location
PDN_PGAx .........................
PASSTHRU .........................
HPx_PDN[1:0].....................
Pin
Speaker Output
SPKMONO=0
SPKMONO=1
SPKSWAP=0
SPKSWAP=1
SPKSWAP=0
SPKSWAP=1
4
SPKOUTA+
SPKOUTB+
SPKOUTA+
SPKOUTB+
6
SPKOUTA-
SPKOUTB-
SPKOUTA+
SPKOUTB+
7
SPKOUTB+
SPKOUTA+
SPKOUTA-
SPKOUTB-
9
SPKOUTB-
SPKOUTA-
SPKOUTB-
Referenced Control
Register Location
SPKMONO..........................
SPKSWAP...........................
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