4.20 S/PDIF Control Register (Index 68h) SPEN S/PDIF Enable. The SPEN bit enables S/PDIF data transmission on the S/PDIF_OUT p" />
參數(shù)資料
型號(hào)： CS4299-JQZ
廠(chǎng)商： Cirrus Logic Inc
文件頁(yè)數(shù)： 25/52頁(yè)
文件大小： 0K
描述： IC CODEC AC 97 W/SRC 48LQFP
標(biāo)準(zhǔn)包裝： 250
系列： SoundFusion™
類(lèi)型： 音頻編解碼器 '97
數(shù)據(jù)接口： 串行
分辨率（位）： 18 b，20 b
ADC / DAC 數(shù)量： 1 / 1
三角積分調(diào)變： 是
動(dòng)態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db)： 85 / 87
電壓 - 電源，模擬： 4.75 V ~ 5.25 V
電壓 - 電源，數(shù)字： 4.75 V ~ 5.25 V
工作溫度： 0°C ~ 70°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 48-LQFP
供應(yīng)商設(shè)備封裝： 48-LQFP（7x7）
包裝： 管件
產(chǎn)品目錄頁(yè)面： 754 (CN2011-ZH PDF)
其它名稱(chēng)： 598-1044
CS4299
31
4.20
S/PDIF Control Register (Index 68h)
SPEN
S/PDIF Enable. The SPEN bit enables S/PDIF data transmission on the S/PDIF_OUT pin.
The SPEN bit routes the left and right channel data from the AC ’97 controller, the digital mix-
er, or the digital effects engine to the S/PDIF transmitter block. The actual data routed to the
S/PDIF block is controlled through the AMAP/SM[1:0] configuration in the AC Mode Control
Register (Index 5Eh).
Val
Validity. The V bit is mapped to the V bit (bit 28) of every sub-frame. If this bit is ‘0’, the signal
is suitable for conversion or processing.
Fs
Sample Rate. The Fs bit indicates the sampling rate for the S/PDIF data. The inverse of this
bit is mapped to bit 25 of the channel status block. When the Fs bit is ‘clear’, the sampling
frequency is 48 kHz. When ‘set’, the sampling frequency is 44.1 kHz. The actual rate at which
S/PDIF data are being transmitted solely depends on the master clock frequency of the
CS4299. The Fs bit is merely an indicator to the S/PDIF receiver.
L
Generation Status. The L bit is mapped to bit 15 of the channel status block. For category
codes 001xxxx, 0111xxx and 100xxxx, a value of ‘0’ indicates original material and a value of
‘1’ indicates a copy of original material. For all other category codes the definition of the L bit
is reversed.
CC[6:0]
Category Code. The CC[6:0] bits are mapped to bits 8-14 of the channel status block.
Emph
Data Emphasis. The Emph bit is mapped to bit 3 of the channel status block. If the Emph bit
is ‘1’, 50/15us filter pre-emphasis is indicated. If the bit is ‘0’, no pre-emphasis is indicated.
Copy
Copyright. The Copy bit is mapped to bit 3 of the channel status block. If the Copy bit is ‘1’
copyright is not asserted and copying is permitted.
/Audio
Audio / Non-Audio. The /Audio bit is mapped to bit 1 of the channel status block. If the /Audio
bit is ‘0’, the data transmitted over S/PDIF is assumed to be digital audio. If the /Audio bit is
‘1’, non-audio data is assumed.
Pro
Professional/Consumer. The Pro bit is mapped to bit 0 of the channel status block. If the Pro
bit is ‘0’, consumer use of the audio control block is indicated. If the bit is ‘1’, professional use
is indicated.
Default
0000h
For a further discussion of the proper use of the channel status bits see application note AN22: Overview of Digital
Audio Interface Data Structures [3].
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
SPEN
Val
0
Fs
L
CC6
CC5
CC4
CC3
CC2
CC1
CC0
Emph
Copy /Audio
Pro
DS319PP6
31
CS4299
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