參數(shù)資料
型號: CS3865CGDWR16
廠商: ZF Electronics Corporation
英文描述: High Performance Dual Channel Current Mode Controller with ENABLE
中文描述: 高性能雙通道電流模式控制器,用ENABLE
文件頁數(shù): 7/8頁
文件大?。?/td> 171K
代理商: CS3865CGDWR16
7
High frequency circuit layout techniques are imperative to
prevent pulse-width jitter. This is usually caused by exces-
sive noise pick-up imposed on the current sense and volt-
age feed-back inputs. Noise immunity can be improved by
lowering circuit impedances at these points. The printed
circuit board layout should contain a ground plane with
low current signal and high current switch and output
grounds returning on separate paths back to the input fil-
ter capacitor. Ceramic bypass capacitors (0.1μF) connected
directly to V
CC
and V
REF
may be required to improve noise
filtering. They provide a low impedance path for filtering
the high frequency noise. All high current loops should be
kept as short as possible using heavy copper runs. The
error amp compensation circuitry and the converter out-
put voltage-divider should be located close to the IC and
as far as possible from the power switch and other noise
generating components.
Design Considerations
Operating Description: continued
+
-
+
+
-
+
+
+
+
-
+
-
+
-
R
T
C
T
V
FB
1
Reference
Regulator
V
UVLO
3.4V
14V
2.5V
R
R
20k
V
REF
Sync
1.0mA
2R
0.5V
250
μ
A
R
1.0mA
2R
Error
Amp 2
COMP
1
ENABLE
2
V
FB
2
COMP
2
Gnd
Pwr Gnd
R
0.5V
Comparator 1
Current Sense
Comparator 1
R
SQ
R
R
S
PWM
PWM
Latch 1
V
UVLO
V
CC
17V
VIN
V
OUT1
V
OUT2
Sense
1
Q1
Q2
R
Sense1
Sense
2
R
Sense2
+
-
+
-
Error
Amp 1
V
OUT
1
V
OUT
2
C
OUT
2
C
OUT
1
5.0V
Q
Oscillator
Internal
Bias
CF1 +
L1
D1
L2
D2
+
+
CF2
R
FB
1
R
FB
2
R
FB
3
R
FB
4
V
OUT
2
V
OUT
1
Dual Boost Regulator
Applications Diagram
C
SYNC
C
T
“SLatch 1
COMP
1
Sense
1
V
OUT1
“ResLatch 1
ENABLE
2
“SLatch 2
COMP
2
Sense
2
“ResLatch 2
V
OUT2
0V
Timing Diagram
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