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參數(shù)資料
| 型號(hào)： | CS3394 |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | SONET/SDH/FEC OC-192 Receiver with EDC Technology |
| 中文描述： | 的SONET / SDH /前向糾錯(cuò)的OC - 192接收器的EDC技術(shù) |
| 文件頁(yè)數(shù)： | 1/2頁(yè) |
| 文件大?。?/td> | 69K |
| 代理商： | CS3394 |
– At a Glan ce –
Product Brief
S3394
SONET/SDH/FEC OC-192 Receiver with EDC Technology
Empowering Intelligent Optical Networks
1
PB1642_v1.01_11/05/03
Description
The S3394 SONET/SDH/FEC Receiver
device is one of the latest additions to
the AMCC DispersionXX
TM
product
family. This device provides full
deserialization capabilities for OC-192
applications and is suitable for
Metropolitan, Long-Haul, Ultra Long-
Haul, and Dense Wavelength Division
Multiplexing (DWDM) networks. The
device performs all necessary serial-to-
parallel functions in conformance with
the SONET/SDH transmission
standards. The standard operating range
is from 9.9 to 11.3 Gbps. AMCCs
proprietary DispersionXX
TM
technology
allows system designers to optimize
coding gain without additional overhead
expansion beyond the standard FEC
data rate of 10.7 Gbps.
Figure 1,
System Block Diagram,
shows
a typical system configuration for the
S3394 device.
Overview
The S3394 device can be used to
implement the front end of SONET/SDH/
FEC equipment which consists primarily
of the serial receive interface. The
system timing circuitry consists of a high-
speed phase detector, clock dividers,
and clock distribution. The devices utilize
on-chip clock synthesis PLL components
that allow the use of a slower external
clock references, 155.52 or 622.08 (plus
FEC rate) MHz, in support of existing
system clocking schemes. The low-jitter,
16-bit, Low Voltage Differential Signaling
(LVDS) interfaces guarantee compliance
with the bit-error rate requirements of the
Telcordia and ITU-T standards.
S3394
AMCC Suggested Interface Devices
Verrazano
(S2509)
Ganges II
(S19202)
Hudson II
(S19203)
Mekong
(S19204)
Khatanga
(S19205)
Niagara
(S19208)
Quad SONET/SDH/Digital Wrapper
Backplane Serdes
STS-192 SONET/SDH Framer
Digital Wrapper - FEC (7% Over-
head)
STS-192 SONET/SDH MUX/
DeMUX with PP
10 GbE MAC and PHY/STS-192c
POS Framer & Mapper
Digital Wrapper/Enhanced FEC
(7% Overhead)
General Features
Operational data rates at 9.9 to
11.3 Gbps
Selectable Electrical RZ or NRZ
Modulation
Dispersion (ISI) compensation
Robust CRU – can extract clock
in low OSNR environments
16-bit OIF Compliant LVDS Data
Path with Programmable Bit
Swap
Integrated low pass filter (coarse/
fine adjust).
Peak detector for input power
monitoring (SSI - Signal Strength
Indicator)
Threshold and phase adjust
capability
Sensitivity 6.0 mV (p-p, SE)
External phase adjust ± 0.30 UI
Linearity gain control – variable
gain adjust
Selectable reference frequency of
155.52 or 622.08 MHz (or various
protocol (+FEC))
Complies with Telcordia/ITU-T/
OIF specifications
3.3 V and 1.8 V power supplies
Compact 15 mm x 15 mm 196 Pin
CBGA Package
Continued on next page...
Figure 1. System Block Diagram
ORX
OTX
ORX
OTX
16
16
16
16
AMCC
NIAGARA/
HUDSON
or
ASIC
MOD
Driver
AMCC
Mux
AMCC
TIA
MOD
Driver
AMCC
Mux
AMCC
TIA
AMCC
NIAGARA/
HUDSON
or
ASIC
AMCC
S3394
RX
AMCC
S3394
RX
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