參數(shù)資料
型號(hào): CS2200-CP-CZZR
廠(chǎng)商: CIRRUS LOGIC INC
元件分類(lèi): XO, clock
英文描述: PHASE LOCKED LOOP, 75 MHz, PDSO10
封裝: 3 MM, LEAD FREE, MO-187, MSOP-10
文件頁(yè)數(shù): 26/26頁(yè)
文件大?。?/td> 307K
代理商: CS2200-CP-CZZR
CS2200-CP
DS759PP1
9
CONTROL PORT SWITCHING CHARACTERISTICS - SPI FORMAT
Inputs: Logic 0 = GND; Logic 1 = VD; CL =20pF.
Notes: 8.
tspi is only needed before first falling edge of CS after power is applied. tspi = 0 at all other times.
9.
Data must be held for sufficient time to bridge the transition time of CCLK.
10. For fcclk < 1 MHz.
Parameter
Symbol
Min
Max
Unit
CCLK Clock Frequency
fccllk
-6
MHz
CCLK Edge to CS Falling
(Note 8)tspi
500
-
ns
CS High Time Between Transmissions
tcsh
1.0
-
s
CS Falling to CCLK Edge
tcss
20
-
ns
CCLK Low Time
tscl
66
-
ns
CCLK High Time
tsch
66
-
ns
CDIN to CCLK Rising Setup Time
tdsu
40
-
ns
CCLK Rising to DATA Hold Time
(Note 9)tdh
15
-
ns
Rise Time of CCLK and CDIN
(Note 10)tr2
-
100
ns
Fall Time of CCLK and CDIN
(Note 10)tf2
-
100
ns
Delay from Supply Voltage Stable to Control Port Ready
tdpor
100
-
s
t
r2
t
f2
t
dsu
t
dh
t
sch
t
scl
CS
CCLK
CDIN
t
css
t
csh
t
spi
tdpor
VD
Figure 3. Control Port Timing - SPI Format (Write Only)
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