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參數(shù)資料
| 型號(hào)： | CS18LV20483AFCR70 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | High Speec Super Low Power SRAM |
| 中文描述： | 高Speec超低功耗SRAM |
| 文件頁數(shù)： | 4/16頁 |
| 文件大小： | 757K |
| 代理商： | CS18LV20483AFCR70 |
High Speed Super Low Power SRAM
256K-Word By 8 Bit
CS18LV20483
PIN DESCRIPTIONS
Name
4
Rev. 1.0
Chiplus reserves the right to change product or specification without notice.
Type
Function
A0 – A17
Input
Address inputs for selecting one of the 262,144 x 8 bit words in the RAM
/CE1, CE2
Input
/CE1 is active LOW and CE2 is active HIGH. Both chip enables must be
active when data read from or write to the device. If either chip enable is
not active, the device is deselected and in a standby power down mode.
The DQ pins will be in high impedance state when the device is
deselected.
/WE
Input
The Write enable input is active LOW. It controls read and write
operations. With the chip selected, when /WE is HIGH and /OE is LOW,
output data will be present on the DQ pins, when /WE is LOW, the data
present on the DQ pins will be written into the selected memory location.
/OE
Input
The output enable input is active LOW. If the output enable is active
while the chip is selected and the write enable is inactive, data will be
present on the DQ pins and they will be enabled. The DQ pins will be in
the high impedance state when /OE is inactive.
DQ0~DQ7
I/O
These 8 bi-directional ports are used to read data from or write data into
the RAM.
Vcc
Power
Power Supply
Gnd
Power
Ground
NC
No connection
TRUTH TABLE
MODE
/CE1
CE2
/WE
X
/OE
DQ0~7
Vcc Current
H
X
X
Standby
X
L
X
L
High Z
I
CCSB
, I
CCSB1
Output
Disabled
Read
Write
L
H
H
H
High Z
I
CC
L
L
H
H
H
L
L
X
D
OUT
D
IN
I
CC
I
CC
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CS18LV20483CCR55 | High Speec Super Low Power SRAM |
| CS18LV20483CCR70 | High Speec Super Low Power SRAM |
| CS18LV20483EIR70 | High Speec Super Low Power SRAM |
| CS18LV20483DCR70 | High Speec Super Low Power SRAM |
| CS18LV20483EIR55 | High Speec Super Low Power SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CS18LV20483AFI-55 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:High Speec Super Low Power SRAM |
| CS18LV20483AFI-70 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:High Speec Super Low Power SRAM |
| CS18LV20483AFIR55 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:High Speec Super Low Power SRAM |
| CS18LV20483AFIR70 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:High Speec Super Low Power SRAM |
| CS18LV20483AZC-55 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:High Speec Super Low Power SRAM |
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