參數(shù)資料
型號： CPS1087
英文描述： Analog IC
中文描述： 模擬IC
文件頁數(shù)： 46/64頁
文件大?。?/td> 870K
代理商： CPS1087
CSP1027 Voice Band Codec for
Cellular Handset and Modem Applications
Data Sheet
January 2002
Agere Systems Inc.
46
7 Application Information
(continued)
7.5.4 Enhanced Oversampling Clock Generation
If system constraints make the requirement of integer
multiples of 125 x the sampling rate (typically integer
multiples of 1.0 MHz) difficult to provide, the CSP1027
can also operate with the ICLK0 internal clock rate at
integer multiples of the sampling rate (typically integer
multiples of 8 kHz). See Section 4.5 on page 16 for
more information.
The following two examples illustrate the usage:
Application Example 4
I
Standard codec application.
I
CLK input clock rate: 2.048 MHz.
I
Codec sampling rate, f
S
: 8 kHz.
Solution:
I
CK
OS
= 125 x 8 kHz = 1.0 MHz, so CLK/CK
OS
=
2.048 or CLK/CK
S
= 2.048 x 125 = 256. Values of M
and N must be found to satisfy this requirement, as
shown below.
I
Set CDIV0 for ÷1 (CDIV0 = 0); hence, f
ICLK
= f
CLK.
I
Using the equations from Section 4.5 on page 16,
Hence, M = 2, S = 1, and N = 6. (Note that if CDIV0
set for ÷ 2, then M = 1, S = +1, and N = 3, which is
not allowed.)
I
Using Tables 2 through 4 on page 18:
CDIV3 = 00 0010.
CDIFS = 0.
CDIF0 = 01 0101.
CDIF1 = 10 0110.
CDIF2 = 0 0000.
Application Example 5
I
IS-54 application.
I
Codec sampling rate, f
S
: 8 kHz.
I
CLK needs to be a common multiple of 8 kHz and
48 x 48.6 kHz.
I
Need phase adjustment.
Solution:
I
48 x 48.6 = 2.3328E6
2.3328E6 ÷ 8E3 = 291.6
To get a common multiple, 291.6 must be multiplied
by a factor to become an integer: 291.6 x 10 = 2916
(an integer). So, CLK/CK
S
= 2916 and CLK/ICLK0 =
2 CLK = 2916 x 8E3 = 23.328E6.
I
CLK input clock rate: 23.328 MHz.
I
Set CDIV0 for ÷2 (CDIV0 = 1) to allow advance/
retard for phase adjustment.
I
ICLK0 internal clock rate is 11.664 MHz.
I
Using the equations from Section 4.5 on page 16,
Hence, M = 12, S = –1, and N = 42.
I
Using Tables 2 through 4 on page 18:
CDIV3 = 00 1100.
CDIFS = 1.
CDIF0 = 00 0011.
CDIF1 = 11 0110.
CDIF2 = 0 0000.
F
S
8 kHz
----------------
125
M
×
(
)
S
2
×
(
)
+
=
F
S
----------------
-----------------------------
256
125
2
×
(
)
1
6
×
(
)
+
=
=
=
F
S
----------------
8 kHz
---------------------------------
1458
125
12
×
(
)
1
–
42
×
(
)
+
=
=
=
相關PDF資料
PDF描述
CPU16RM M68HC16 Family CPU16 Reference Manual
CQ202-4M 4.0 AMP TRIAC 600 THRU 800 VOLTS
CQ202-4B TRIAC|200V V(DRM)|4A I(T)RMS|TO-202
CQ202-4B2 TRIAC|200V V(DRM)|4A I(T)RMS|TO-202VAR
CQ202-4BS2 TRIAC|200V V(DRM)|4A I(T)RMS|TO-202VAR
相關代理商/技術參數(shù)
參數(shù)描述
CPS1087A 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC
CPS1087B 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC
CPS1088 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC
CPS1089 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC
CPS1090 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*