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參數(shù)資料
| 型號： | CPPC7L-A5BP-4.0000MHZTS |
| 廠商： | CARDINAL COMPONENTS INC |
| 元件分類： | XO, clock |
| 英文描述： | CRYSTAL OSCILLATOR, CLOCK, 4 MHz, CMOS/TTL OUTPUT |
| 封裝： | CERAMIC, SMD, 4 PIN |
| 文件頁數(shù)： | 4/5頁 |
| 文件大?。?/td> | 3390K |
| 代理商： | CPPC7L-A5BP-4.0000MHZTS |
CARDINAL COMPONENTS
CARDINAL COMPONENTS
Description
TEST CONDITIONS
Min
Typ
Max Unit
Duty Cycle:
TTL @ 1.4 V
< 50 MHz, CL = 50 pF
45
55
%
4.5-5.5 Vdd
50–66 MHz, CL = 15 pF
45
55
%
66–125 MHz, CL = 25 pF
40
60
%
125–133 MHz, CL = 15 pF
40
60
%
Duty Cycle:
< 66 MHz, CL < 25 pF
45
55
%
CMOS @ Vdd/2
66–125 MHz, CL < 25 pF
40
60
%
4.5-5.5 Vdd
125–133 MHz, CL < 15 pF
40
60
%
3.0–3.6 Vdd
< 40 MHz, CL < 30 pF
45
55
%
40-100 MHz, CL < 15 pF
40
60
%
Output Clock Rise/Fall
0.8V–2.0V, 4.5-5.5 Vdd, CL = 50
1.8
ns
0.8V–2.0V, 4.5-5.5 Vdd, CL = 25
1.2
ns
0.8V–2.0V, 4.5-5.5 Vdd, CL = 15
0.9
ns
0.2–0.8Vdd, 4.5-5.5 Vdd, CL = 50
3.4
ns
0.2–0.8Vdd, 3.0–3.6 Vdd, CL = 30
4.0
ns
0.2–0.8Vdd, 3.0–3.6 Vdd, CL = 15
2.4
ns
Start Up Time
From power on
2
ms
Power Down Delay Time
Synchronous
PWR_DWN pin LOW to output Hi-Z
T/2
T+10
ns
Asynchronous
10
15
ns
Output Disable Time
Synchronous
OE pin LOW to output Hi-Z
T/2
T+10
ns
Asynchronous
T = Frequency oscillator period
10
15
ns
Output Enable Time
100
ns
< 33.000 MHz
40
50
ps
> 33.000, MHz
30
40
ps
Peak to Peak *
< 33.000 MHz
100
250
ps
> 33.000 MHz
75
175
ps
Series CPP
Output Clock Switching Characteristics
* Jitter tested at > 1,000,000 samples, exceeding JEDEC std JESD65.
Field Programmable Blank Oscillator
instrument within seconds
Can be programmed twice
Programmed with the PG-3000, PG-3100 field oscillator programming
Standard Package Options
RMS Period Jitter:
Cardinal Components, Inc.
155 Route 46 West
Wayne, NJ 07470
Rev: C-090414-11
TEL:
(973)785-1333
E-MAIL: sales@cardinalxtal.com
WEB:
http://www.cardinalxtal.com
O-36
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