參數(shù)資料
型號： CP82C50A-5
廠商： HARRIS SEMICONDUCTOR
元件分類： 微控制器/微處理器
英文描述： CMOS Asynchronous Communications Element
中文描述： 1 CHANNEL(S), 625K bps, SERIAL COMM CONTROLLER, PDIP40
文件頁數(shù)： 1/21頁
文件大小： 101K
代理商： CP82C50A-5
1
March 1997
82C50A
CMOS Asynchronous
Communications Element
Features
Single Chip UART/BRG
DC to 625K Baud (DC to 10MHz Clock)
Crystal or External Clock Input
On Chip Baud Rate Generator 1 to 65535 Divisor
Generates 16X Clock
Prioritized Interrupt Mode
Fully TTL/CMOS Compatible
Microprocessor Bus Oriented Interface
80C86/80C88 Compatible
Scaled SAJI IV CMOS Process
Low Power - 1mA/MHz Typical
Modem Interface
Line Break Generation and Detection
Loopback and Echo Modes
Doubled Buffered Transmitter and Receiver
Single 5V Supply
Ordering Information
Description
The 82C50A Asynchronous Communication Element (ACE)
is a high performance programmable Universal Asynchro-
nous Receiver/Transmitter (UART) and Baud Rate Genera-
tor (BRG) on a single chip. Using Intersil’s advanced Scaled
SAJI IV CMOS Process, the ACE will support data rates
from DC to 625K baud (0-10MHz clock).
The ACE’s receiver circuitry converts start, data, stop, and
parity bits into a parallel data word. The transmitter circuitry
converts a parallel data word into serial form and appends
the start, parity, and stop bits. The word length is program-
mable to 5, 6, 7, or 8 data bits. Stop bit selection provides a
choice of 1,1.5, or 2 stop bits.
The Baud Rate Generator divides the clock by a divisor
programmable from 1 to 2
16
-1 to provide standard RS-232C
baud rates when using any one of three industry standard
baud rate crystals (1.8432MHz, 2.4576MHz, or 3.072MHz).
A programmable buffered clock output (BAUDOUT) provides
either a buffered oscillator or 16X (16 times the data rate)
baud rate clock for general purpose system use.
To meet the system requirements of a CPU interfacing to an
asynchronous channel, the modem control signals RTS,
CTS, DSR, DTR, RI, DCD are provided. Inputs and outputs
have been designed with full TTL/CMOS compatibility in
order to facilitate mixed TTL/NMOS/CMOS system design.
Functional Diagram
PACKAGE
PDIP
TEMPERATURE
RANGE (
o
C)
0 to +70
-40 to +85
0 to +70
-40 to +85
0 to +70
-40 to +85
-55 to +125
625K BAUD
CP82C50A-5
IP82C50A-5
CS82C50A-5
IS82C50A-5
CD82C50A-5
ID82C50A-5
MD82C50A-5/B
PKG.
NO.
E40.6
E40.6
N44.65
N44.65
F40.6
F40.6
F40.6
PLCC
CERDIP
D0
D1
D2
D3
D4
D5
D6
D7
1
2
3
4
5
6
7
8
A0
A1
A2
MR
DISTR
DISTR
DOSTR
DOSTR
28
27
26
35
22
21
19
18
CSO
CS1
CS2
12
13
14
ADS
25
MICROPROCESSOR INTERFACE
INTERRUPT
ENABLE,
ID, & CONTROL
30
INTRPT
23
DDIS
24
CSOUT
10
9
15 BAUDOUT
SIN
UART
MODEM
DIVISOR LATCH
AND BAUD RATE
GENERATOR
MODEM CONTROL
MODEM STATUS
RECEIVER
TRANSMITTER
RCLK
16
17
XTAL1
XTAL2
11
32
33
SOUT
RTS
DTR
34
OUT1
OUT2
CTS
DSR
DCD
31
36
37
38
39
RI
LINE STATUS
AND CONTROL
File Number
2958.1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
|
Copyright
Intersil Corporation 1999
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