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參數(shù)資料
| 型號： | CP7FREQNAT0 |
| 廠商： | CTS CORP |
| 元件分類： | XO, clock |
| 英文描述： | CRYSTAL OSCILLATOR, CLOCK, 2 MHz - 200 MHz, LVCMOS OUTPUT |
| 封裝： | GREEN, LCC, CERAMIC PACKAGE-4 |
| 文件頁數(shù)： | 2/4頁 |
| 文件大小： | 116K |
| 代理商： | CP7FREQNAT0 |
Document No. 008-0321-0
Page 2 - 4
Rev. B
CTS Electronic Components, Inc. 171 Covington Drive Bloomingdale, IL 60108
Model CP5 and CP7
5x3.2mm and 7x5mm Low Cost
Programmable Clock Oscillator
ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNIT
Maximum Supply Voltage
VCC
-
-0.5
-
4.6
V
Storage Temperature
TSTG
-
-55
-
125
°C
Frequency Range
fO
-
2
-
200
MHz
Frequency Stability
(See Note 1 and Ordering Information)
Operating Temperature
Commercial
-20
70
Industrial
-40
85
Data Retention
-
@ 85°C
10
-
Years
Supply Voltage
(see Note 2)
2.25
2.5
2.75
2.97
3.3
3.63
Supply Current
ICC
@ CL = 15 pF
-
-40
mA
Output Load
CL
--
-
15
pF
Output Voltage Levels
Logic '1' Level
VOH
CMOS Load
IOH = -4mA
0.1VCC
--
Logic '0' Level
VOL
CMOS Load
IOL = +4mA
--
0.9VCC
Output Duty Cycle
SYM
@ 50% Level
45
-
55
%
Rise and Fall Time
TR, TF
@ 20% - 80% Levels
-
2.5
4
ns
Start Up Time
TS
Application of VCC
--
10
ms
Enable Function
Enable Input Voltage
VIH
Pin 1 Logic '1', Output Enabled
0.7VCC
--
Disable Input Voltage
VIL
Pin 1 Logic '0', Output Disabled
-
0.2VCC
Standby Current
IST
Pin 1 Logic '0', Output Disabled
-
10
uA
Enable Start Up Time
TPLZ
Pin 1 Logic '1', Output Enabled
-
10
ms
Jitter (peak - peak)
JP-P
10k hits & 0.1uF bypass capacitor
-
100
250
ps
Phase Jitter
tjms
Bandwidth 12 kHz - 20 MHz
-
2.5
-
ps RMS
Notes:
1.
2. Power supply start-up time should be greater than 150 us (0%VCC to 90%VCC).
Inclusive of initial tolerance at time of shipment, changes in supply voltage, load, temperature and first year aging at an average
operating temperature of +40 °C.
-50
V
TA
-°C
25
f/fO
E
lec
tr
ic
al
and
W
avefo
rm
P
aramet
ers
VCC
± 10 %
V
± ppm
-
Abso
lut
eMa
ximums
CMOS/TTL OUTPUT WAVEFORM
PERIOD (T)
90%, 80%, 2.4V
50%, 1.5V
10%, 20%, 0.5V
DUTY CYCLE = t/T x 100 (%)
V
OH
OL
Tr
Tf
UPTIME (t)
TEST CIRCUIT, CMOS LOAD
POWER
SUPPLY
+
-
+-
-
+
VM
mA
.01uF
D.U.T.
43
12
C L
Including probe
capacitance.
Enable Input
ENABLE TRUTH TABLE
PIN 1
PIN 3
Logic ‘1’
Output
Open
Output
Logic ‘0’
High Imp.
D.U.T. PIN ASSIGNMENTS
PIN
SYMBOL
DESCRIPTION
1
EOH
Enable Input (Standby)
2
GND
Circuit & Package Ground
3
Output
RF Output
4
VCC
Supply Voltage
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