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參數(shù)資料
| 型號(hào)： | COREWARE |
| 英文描述： | CoreWare Merlin2 Fibre Channel core family |
| 中文描述： | CoreWare Merlin2光纖通道核心家庭 |
| 文件頁(yè)數(shù)： | 3/6頁(yè) |
| 文件大?。?/td> | 108K |
| 代理商： | COREWARE |
Loop Port Controller
The Loop Port Controller is responsible for performing
the loop protocols such as loop initialization, arbitration
and the opening and closing of loop circuits. The Loop
Port Controller’s FC-AL2 Loop Port State Machine
implements the FC-1 and FC-AL2 layers of the Fibre
Channel standard. The integrated GigaBlaze
Transceiver
provides the Fibre Channel FC-0 layer physical interface.
The 1.0625 Gb/s transceivers are based on LSI Logic’s
widely adopted GigaBlaze
embedded transceiver
technology. The GigaBlaze
core is a gigabit per second
transceiver, which is compliant with the Fibre Channel
FC-0 physical interface standard. The transceiver core
includes serializer and deserializer circuitry. The
deserializer receives a serial gigabit speed input data
stream and converts it into parallel. This parallel data is
received by the Merlin
cores 8B/10B decode circuitry.
Likewise, parallel data from Merlin’s 8B/10B encoder can
be transmitted at the Fibre Channel physical rate of
1.0625 Gb/s after being converted into a serial stream by
the serializer. GigaBlaze
SeriaLink technology greatly
reduces cost, power consumption and board area over
system implementations using external bipolar or gallium
arsenide transceivers.
Figure 3: Loop Port Controller
3
Figure 4: Single Port Fibre Channel Controller -
Combines the Loop Port Controller, a Fibre Channel Engine and the Bolt-On Modules
Implementation Description
The Merlin
Fibre Channel Core Family is used in three
basic configurations: Loop Port Controller, Single Port
and Dual Loop. The Loop Port Controller can be
used alone for a cost-effective solution in applications
such as Switches/Hubs (see Figure 3). The Single Port
and Dual Loop configurations add a high-performance
Fibre Channel protocol engine which handles Fibre
Channel exchange, sequence and frame management (see
Figures 4 & 5). Once programmed with control
information for a Fibre Channel exchange, the Single Port
and Dual Loop configurations automate the exchange
from start to finish. The Single Port and Dual Loop
configurations also provide hardware assistance for FCP
SCSI Initiator and Target operations including
notification of incoming SCSI commands and responses
and XFER_RDY management. Two single port
configurations can be combined to create a dual port
configuration (see Figure 6).
The Merlin
Fibre Channel Core Family is architected
for scalability, enabling both high-performance and
low-cost Fibre Channel implementations. You can
choose on-chip frame buffer sizes to maintain Fibre
Channel performance with a wide range of back-end
bus structures. Implementers can tune the number of
exchange contexts and incoming/outgoing frames cached
concurrently on chip to meet varying performance
requirements. The Merlin Fibre Channel Core Family
has high-speed bus interfaces, which eliminate bottlenecks
in the Fibre Channel data path. Available 32-, 64- and
128-bit interfaces handle frame delivery between the cores
and downstream logic. A 32-bit local bus is provided for
designs requiring a local microprocessor, such as LSI
Logic’s MiniRISC, TinyRISC and ARM cores, or RAM.
End-to-end flow through parity protection is provided
on all Merlin
core data paths. The Merlin
core family
simplifies the design debug process by providing
extensive core visibility through the local bus interface.
Decode
E
1
Encode
LPC
Loop
Port
State
Machine
Transmit
Exchange
Controller
Transmit Buffer (TXB)
Register
File
FCP
SCSI
Assist
Receive
Exchange
Controller
Processor
Interface
Fibre Channel Engine
Bolt-On Modules
Decode
E
1
Encode
LPC
Receive Buffer (RXB)
T
P
B
M
E
T
T
R
Loop
Port
State
Machine
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