參數(shù)資料
    

    


    


    
型號(hào)：
COP8SGH540Q3

    

    
廠商：
National Semiconductor Corporation

    

    
英文描述：
8-Bit CMOS ROM Based and OTP Microcontrollers with 8k to 32k Memory, Two Comparators and USART

    

    
中文描述：
8位的CMOS基于ROM和OTP微控制器具有8K到32K的內(nèi)存，2個(gè)比較器和USART

    

    
文件頁數(shù)：
30/62頁

    

    
文件大?。?/td>
913K

    

    
代理商：
COP8SGH540Q3


    

    

    

	
    
    
    

    
    
	
    8.0 USART
    (Continued)
    8.3 Associated I/O Pins
    Data is transmitted on the TDX pin and received on the RDX
    pin. TDX is the alternate function assigned to Port L pin L2;
    it is selected by setting ETDX (in the ENUI register) to one.
    RDX is an inherent function of Port L pin L3, requiring no
    setup.
    The baud rate clock for the USART can be generated on-
    chip, or can be taken from an external source. Port L pin L1
    (CKX) is the external clock I/O pin. The CKX pin can be
    either an input or an output, as determined by Port L Con-
    figuration and Data registers (Bit 1). As an input, it accepts a
    clock signal which may be selected to drive the transmitter
    and/or receiver. As an output, it presents the internal Baud
    Rate Generator output.
    8.4 USART Operation
    The USART has two modes of operation: asynchronous
    mode and synchronous mode.
    8.4.1 ASYNCHRONOUS MODE
    This mode is selected by resetting the SSEL (in the ENUI
    register) bit to zero. The input frequency to the USART is 16
    times the baud rate.
    The TSFT and TBUF registers double-buffer data for trans-
    mission. While TSFT is shifting out the current character on
    the TDX pin, the TBUF register may be loaded by software
    with the next byte to be transmitted. When TSFT finishes
    transmitting the current character the contents of TBUF are
    transferred to the TSFT register and the Transmit Buffer
    Empty Flag (TBMT in the ENU register) is set. The TBMT
    flag is automatically reset by the USART when software
    loads a new character into the TBUF register. There is also
    the XMTG bit which is set to indicate that the USART is
    transmitting. This bit gets reset at the end of the last frame
    (end of last Stop bit). TBUF is a read/write register.
    The RSFT and RBUF registers double-buffer data being
    received. The USART receiver continually monitors the sig-
    nal on the RDX pin for a low level to detect the beginning of
    a Start bit. Upon sensing this low level, it waits for half a bit
    time and samples again. If the RDX pin is still low, the
    receiver considers this to be a valid Start bit, and the remain-
    ing bits in the character frame are each sampled a single
    time, at the mid-bit position. Serial data input on the RDX pin
    is shifted into the RSFT register. Upon receiving the com-
    plete character, the contents of the RSFT register are copied
    into the RBUF register and the Received Buffer Full Flag
    (RBFL) is set. RBFL is automatically reset when software
    reads the character from the RBUF register. RBUF is a read
    only register. There is also the RCVG bit which is set high
    when a framing error occurs and goes low once RDX goes
    high. TBMT, XMTG, RBFL and RCVG are read only bits.
    8.4.2 SYNCHRONOUS MODE
    In this mode data is transferred synchronously with the
    clock. Data is transmitted on the rising edge and received on
    the falling edge of the synchronous clock.
    This mode is selected by setting SSEL bit in the ENUI
    register. The input frequency to the USART is the same as
    the baud rate.
    When an external clock input is selected at the CKX pin, data
    transmit and receive are performed synchronously with this
    clock through TDX/RDX pins.
    If data transmit and receive are selected with the CKX pin as
    clock output, the device generates the synchronous clock
    output at the CKX pin. The internal baud rate generator is
    used to produce the synchronous clock. Data transmit and
    receive are performed synchronously with this clock.
    8.5 FRAMING FORMATS
    The USART supports several serial framing formats (Figure
    22). The format is selected using control bits in the ENU,
    ENUR and ENUI registers.
    The first format (1, 1a, 1b, 1c) for data transmission (CHL0 =
    1, CHL1 = 0) consists of Start bit, seven Data bits (excluding
    parity) and 7/8, one or two Stop bits. In applications using
    parity, the parity bit is generated and verified by hardware.
    The second format (CHL0 = 0, CHL1 = 0) consists of one
    Start bit, eight Data bits (excluding parity) and 7/8, one or
    two Stop bits. Parity bit is generated and verified by hard-
    ware.
    The third format for transmission (CHL0 = 0, CHL1 = 1)
    consists of one Start bit, nine Data bits and 7/8, one or two
    Stop bits. This format also supports the USART “ATTEN-
    TION” feature. When operating in this format, all eight bits of
    TBUF and RBUF are used for data. The ninth data bit is
    transmitted and received using two bits in the ENU and
    ENUR registers, called XBIT9 and RBIT9. RBIT9 is a read
    only bit. Parity is not generated or verified in this mode.
    For any of the above framing formats, the last Stop bit can
    be programmed to be 7/8th of a bit in length. If two Stop bits
    are selected and the 7/8th bit is set (selected), the second
    Stop bit will be 7/8th of a bit in length.
    The parity is enabled/disabled by PEN bit located in the ENU
    register. Parity is selected for 7- and 8-bit modes only. If
    parity is enabled (PEN = 1), the parity selection is then
    performed by PSEL0 and PSEL1 bits located in the ENU
    register.
    Note that the XBIT9/PSEL0 bit located in the ENU register
    serves two mutually exclusive functions. This bit programs
    the ninth bit for transmission when the USART is operating
    with nine data bits per frame. There is no parity selection in
    this framing format. For other framing formats XBIT9 is not
    needed and the bit is PSEL0 used in conjunction with PSEL1
    to select parity.
    The frame formats for the receiver differ from the transmitter
    in the number of Stop bits required. The receiver only re-
    quires one Stop bit in a frame, regardless of the setting of the
    Stop bit selection bits in the control register. Note that an
    implicit assumption is made for full duplex USART operation
    that the framing formats are the same for the transmitter and
    receiver.
    C
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    相關(guān)代理商/技術(shù)參數(shù)
    		

    參數(shù)描述
    		

    
    

    
COP8SGR728M7
功能描述:8位微控制器 -MCU RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT

    

    
COP8SGR728M7/NOPB
功能描述:8位微控制器 -MCU RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT

    

    
COP8SGR728M8
功能描述:8位微控制器 -MCU RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT

    

    
COP8SGR728M8/NOPB
功能描述:8位微控制器 -MCU RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT

    

    
COP8SGR728N8
功能描述:8位微控制器 -MCU RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT

    

    
    
    
    
	
    	
    
    
     
     
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