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    參數(shù)資料
    型號(hào): COP8SGG740M7
    廠商: National Semiconductor Corporation
    英文描述: 8-Bit CMOS ROM Based and OTP Microcontrollers with 8k to 32k Memory, Two Comparators and USART
    中文描述: 8位的CMOS基于ROM和OTP微控制器具有8K到32K的內(nèi)存,2個(gè)比較器和USART
    文件頁(yè)數(shù): 31/62頁(yè)
    文件大小: 913K
    代理商: COP8SGG740M7
    8.0 USART
    (Continued)
    8.6 USART INTERRUPTS
    The USART is capable of generating interrupts. Interrupts
    are generated on Receive Buffer Full and Transmit Buffer
    Empty. Both interrupts have individual interrupt vectors. Two
    bytes of program memory space are reserved for each in-
    terrupt vector. The two vectors are located at addresses
    0xEC to 0xEF Hex in the program memory space. The
    interrupts can be individually enabled or disabled using En-
    able Transmit Interrupt (ETI) and Enable Receive Interrupt
    (ERI) bits in the ENUI register.
    The interrupt from the Transmitter is set pending, and re-
    mains pending, as long as both the TBMT and ETI bits are
    set. To remove this interrupt, software must either clear the
    ETI bit or write to the TBUF register (thus clearing the TBMT
    bit).
    The interrupt from the receiver is set pending, and remains
    pending, as long as both the RBFL and ERI bits are set. To
    remove this interrupt, software must either clear the ERI bit
    or read from the RBUF register (thus clearing the RBFL bit).
    8.7 Baud Clock Generation
    The clock inputs to the transmitter and receiver sections of
    the USART can be individually selected to come either from
    an external source at the CKX pin (port L, pin L1) or from a
    source selected in the PSR and BAUD registers. Internally,
    the basic baud clock is created from the oscillator frequency
    through a two-stage divider chain consisting of a 1–16 (in-
    crements of 0.5) prescaler and an 11-bit binary counter.
    (Figure 23). The divide factors are specified through two
    read/write registers shown in Figure 24 Note that the 11-bit
    Baud Rate Divisor spills over into the Prescaler Select Reg-
    ister (PSR). PSR is cleared upon reset.
    As shown in Table 5 a Prescaler Factor of 0 corresponds to
    NO CLOCK. This condition is the USART power down mode
    where the USART clock is turned off for power saving pur-
    pose. The user must also turn the USART clock off when a
    different baud rate is chosen.
    The correspondences between the 5-bit Prescaler Select
    and Prescaler factors are shown in Table 5 There are many
    ways to calculate the two divisor factors, but one particularly
    effective method would be to achieve a 1.8432 MHz fre-
    quency coming out of the first stage. The 1.8432 MHz pres-
    caler output is then used to drive the software programmable
    baud rate counter to create a 16x clock for the following baud
    rates: 110, 134.5, 150, 300, 600, 1200, 1800, 2400, 3600,
    4800, 7200, 9600, 19200 and 38400 (Table 4). Other baud
    10131740
    FIGURE 22. Framing Formats
    C
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    31
    相關(guān)PDF資料
    PDF描述
    COP8SGG740M8 8-Bit CMOS ROM Based and OTP Microcontrollers with 8k to 32k Memory, Two Comparators and USART
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    COP8SGG740N3 Tantalum Conformal-Coated Capacitor; Capacitance: 100uF; Voltage: 6.3V; Case Size: 2x3.6 mm; Packaging: Tape & Reel
    COP8SGG740N6 Tantalum Conformal-Coated Capacitor; Capacitance: 100uF; Voltage: 6.3V; Packaging: Tape & Reel
    COP8SGG740N7 Tantalum Conformal-Coated Capacitor; Capacitance: 100uF; Voltage: 6.3V; Case Size: 3.5x2.7 mm; Packaging: Tape & Reel
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    參數(shù)描述
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