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| 型號： | COP8SGE744V8XXX |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 15 MHz, MICROCONTROLLER, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 46/62頁 |
| 文件大?。?/td> | 840K |
| 代理商： | COP8SGE744V8XXX |
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14.0 Instruction Set (Continued)
14.4.9 No-Operation Instruction
The no-operation instruction does nothing, except to occupy
space in the program memory and time in execution.
No-Operation (NOP)
Note: The VIS is a special case of the Indirect Transfer of Control addressing
mode, where the double byte vector associated with the interrupt is
transferred from adjacent addresses in the program memory into the
program counter (PC) in order to jump to the associated interrupt
service routine.
14.5 REGISTER AND SYMBOL DEFINITION
The following abbreviations represent the nomenclature
used
in
the
instruction
description
and
the
COP8
cross-assembler.
Registers
A
8-Bit Accumulator Register
B
8-Bit Address Register
X
8-Bit Address Register
SP
8-Bit Stack Pointer Register
PC
15-Bit Program Counter Register
PU
Upper 7 Bits of PC
PL
Lower 8 Bits of PC
Registers
C
1 Bit of PSW Register for Carry
HC
1 Bit of PSW Register for Half Carry
GIE
1 Bit of PSW Register for Global Interrupt
Enable
VU
Interrupt Vector Upper Byte
VL
Interrupt Vector Lower Byte
Symbols
[B]
Memory Indirectly Addressed by B Register
[X]
Memory Indirectly Addressed by X Register
MD
Direct Addressed Memory
Mem
Direct Addressed Memory or [B]
Meml
Direct Addressed Memory or [B] or
Immediate Data
Imm
8-Bit Immediate Data
Reg
Register Memory: Addresses F0 to FF
(Includes B, X and SP)
Bit
Bit Number (0 to 7)
←
Loaded with
Exchanged with
14.6 INSTRUCTION SET SUMMARY
ADD
A,Meml
ADD
A←A + Meml
ADC
A,Meml
ADD with Carry
A←A+Meml+C,C←Carry,
HC←Half Carry
SUBC
A,Meml
Subtract with Carry
A←AMemI+C,C←Carry,
HC←Half Carry
AND
A,Meml
Logical AND
A←A and Meml
ANDSZ
A,Imm
Logical AND Immed., Skip if Zero
Skip next if (A and Imm) = 0
OR
A,Meml
Logical OR
A←A or Meml
XOR
A,Meml
Logical EXclusive OR
A←A xor Meml
IFEQ
MD,Imm
IF EQual
Compare MD and Imm, Do next if MD = Imm
IFEQ
A,Meml
IF EQual
Compare A and Meml, Do next if A = Meml
IFNE
A,Meml
IF Not Equal
Compare A and Meml, Do next if A
≠ Meml
IFGT
A,Meml
IF Greater Than
Compare A and Meml, Do next if A > Meml
IFBNE
#
If B Not Equal
Do next if lower 4 bits of B
≠ Imm
DRSZ
Reg
Decrement Reg., Skip if Zero
Reg←Reg 1, Skip if Reg = 0
SBIT
#,Mem
Set BIT
1 to bit, Mem (bit = 0 to 7 immediate)
RBIT
#,Mem
Reset BIT
0 to bit, Mem
IFBIT
#,Mem
IF BIT
If bit #, A or Mem is true do next instruction
RPND
Reset PeNDing Flag
Reset Software Interrupt Pending Flag
X
A,Mem
EXchange A with Memory
A
Mem
X
A,[X]
EXchange A with Memory [X]
A
[X]
LD
A,Meml
LoaD A with Memory
A←Meml
LD
A,[X]
LoaD A with Memory [X]
A←[X]
LD
B,Imm
LoaD B with Immed.
B←Imm
LD
Mem,Imm
LoaD Memory Immed.
Mem←Imm
LD
Reg,Imm
LoaD Register Memory Immed.
Reg←Imm
XA, [B ±]
EXchange A with Memory [B]
A
[B], (B←B ±1)
XA, [X ±]
EXchange A with Memory [X]
A
[X], (X←X ±1)
COP8SG
Family
www.national.com
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