- 您現在的位置：買賣IC網 > PDF目錄379985 > COP8SGE628Q6 (National Semiconductor Corporation) 8-Bit CMOS ROM Based and OTP Microcontrollers with 8k to 32k Memory, Two Comparators and USART PDF資料下載
參數資料
| 型號： | COP8SGE628Q6 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | 8-Bit CMOS ROM Based and OTP Microcontrollers with 8k to 32k Memory, Two Comparators and USART |
| 中文描述： | 8位的CMOS基于ROM和OTP微控制器具有8K到32K的內存，2個比較器和USART |
| 文件頁數： | 41/62頁 |
| 文件大?。?/td> | 913K |
| 代理商： | COP8SGE628Q6 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁當前第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁
11.0 WATCHDOG/Clock Monitor
Each device contains a user selectable WATCHDOG and
clock monitor. The following section is applicable only if
WATCHDOG feature has been selected in the ECON regis-
ter. The WATCHDOG is designed to detect the user program
getting stuck in infinite loops resulting in loss of program
control or “runaway” programs.
The WATCHDOG logic contains two separate service win-
dows. While the user programmable upper window selects
the WATCHDOG service time, the lower window provides
protection against an infinite program loop that contains the
WATCHDOG service instruction.
The Clock Monitor is used to detect the absence of a clock or
a very slow clock below a specified rate on the CKI pin.
The WATCHDOG consists of two independent logic blocks:
WD UPPER and WD LOWER. WD UPPER establishes the
upper limit on the service window and WD LOWER defines
the lower limit of the service window.
Servicing the WATCHDOG consists of writing a specific
value to a WATCHDOG Service Register named WDSVR
which is memory mapped in the RAM. This value is com-
posed of three fields, consisting of a 2-bit Window Select, a
5-bit Key Data field, and the 1-bit Clock Monitor Select field.
Table 7 shows the WDSVR register.
TABLE 7. WATCHDOG Service Register (WDSVR)
Window
Select
X
7
Key Data
Clock
Monitor
Y
0
X
6
0
5
1
4
1
3
0
2
0
1
The lower limit of the service window is fixed at 2048 instruc-
tion cycles. Bits 7 and 6 of the WDSVR register allow the
user to pick an upper limit of the service window.
Table 8 shows the four possible combinations of lower and
upper limits for the WATCHDOG service window. This flex-
ibility in choosing the WATCHDOG service window prevents
any undue burden on the user software.
Bits 5, 4, 3, 2 and 1 of the WDSVR register represent the
5-bit Key Data field. The key data is fixed at 01100. Bit 0 of
the WDSVR Register is the Clock Monitor Select bit.
TABLE 8. WATCHDOG Service Window Select
WDSVR WDSVR
Bit 7
0
0
1
1
x
x
Clock
Monitor
x
x
x
x
0
1
Service Window
(Lower-Upper Limits)
2048–8k t
C
Cycles
2048–16k t
C
Cycles
2048–32k t
C
Cycles
2048–64k t
C
Cycles
Clock Monitor Disabled
Clock Monitor Enabled
Bit 6
0
1
0
1
x
x
11.1 CLOCK MONITOR
The Clock Monitor aboard the device can be selected or
deselected under program control. The Clock Monitor is
guaranteed not to reject the clock if the instruction cycle
clock (1/t
) is greater or equal to 10 kHz. This equates to a
clock input rate on CKI of greater or equal to 100 kHz.
11.2 WATCHDOG/CLOCK MONITOR OPERATION
The WATCHDOG is enabled by bit 2 of the ECON register.
When this ECON bit is 0, the WATCHDOG is enabled and
pin G1 becomes the WATCHDOG output with a weak pullup.
The WATCHDOG and Clock Monitor are disabled during
reset. The device comes out of reset with the WATCHDOG
armed, the WATCHDOG Window Select bits (bits 6, 7 of the
WDSVR Register) set, and the Clock Monitor bit (bit 0 of the
WDSVR Register) enabled. Thus, a Clock Monitor error will
occur after coming out of reset, if the instruction cycle clock
frequency has not reached a minimum specified value, in-
cluding the case where the oscillator fails to start.
The WDSVR register can be written to only once after reset
and the key data (bits 5 through 1 of the WDSVR Register)
register involves two irrevocable choices: (i) the selection of
the WATCHDOG service window (ii) enabling or disabling of
the Clock Monitor. Hence, the first write to WDSVR Register
involves selecting or deselecting the Clock Monitor, select
the WATCHDOG service window and match the WATCH-
DOG key data. Subsequent writes to the WDSVR register
will compare the value being written by the user to the
WATCHDOG service window value and the key data (bits 7
through 1) in the WDSVR Register. Table 9 shows the se-
quence of events that can occur.
The user must service the WATCHDOG at least once before
the upper limit of the service window expires. The WATCH-
DOG may not be serviced more than once in every lower
limit of the service window.
The WATCHDOG has an output pin associated with it. This
is the WDOUT pin, on pin 1 of the port G. WDOUT is active
low and must be externally connected to the RESET pin or to
some other external logic which handles WATCHDOG event.
The WDOUT pin has a weak pullup in the inactive state. This
pull-up is sufficient to serve as the connection to V
for
systems which use the internal Power On Reset. Upon
triggering the WATCHDOG, the logic will pull the WDOUT
(G1) pin low for an additional 16 t
–32 t
cycles after the
signal level on WDOUT pin goes below the lower Schmitt
trigger threshold. After this delay, the device will stop forcing
the WDOUT output low. The WATCHDOG service window
will restart when the WDOUT pin goes high.
AWATCHDOG service while the WDOUT signal is active will
be ignored. The state of the WDOUT pin is not guaranteed
on reset, but if it powers up low then the WATCHDOG will
time out and WDOUT will go high.
The Clock Monitor forces the G1 pin low upon detecting a
clock frequency error. The Clock Monitor error will continue
until the clock frequency has reached the minimum specified
value, after which the G1 output will go high following 16
t
–32 t
clock cycles. The Clock Monitor generates a con-
tinual Clock Monitor error if the oscillator fails to start, or fails
to reach the minimum specified frequency. The specification
for the Clock Monitor is as follows:
1/t
C
>
10 kHz—No clock rejection.
1/t
C
<
10 Hz—Guaranteed clock rejection.
C
www.national.com
41
相關PDF資料 |
PDF描述 |
|---|---|
| COP8SGE728D8 | 8-Bit CMOS ROM Based and OTP Microcontrollers with 8k to 32k Memory, Two Comparators and USART |
| COP8SGE728D9 | 8-Bit CMOS ROM Based and OTP Microcontrollers with 8k to 32k Memory, Two Comparators and USART |
| COP8SGE728L3 | 8-Bit CMOS ROM Based and OTP Microcontrollers with 8k to 32k Memory, Two Comparators and USART |
| COP8SGE728L6 | 8-Bit CMOS ROM Based and OTP Microcontrollers with 8k to 32k Memory, Two Comparators and USART |
| COP8SGE728L7 | 8-Bit CMOS ROM Based and OTP Microcontrollers with 8k to 32k Memory, Two Comparators and USART |
相關代理商/技術參數 |
參數描述 |
|---|---|
| COP8SGE728M7/NOPB | 制造商:Texas Instruments 功能描述:MCU 8-Bit COP8 CISC 8KB EPROM 3.3V/5V 28-Pin SOIC W Rail |
| COP8SGE728M8 | 功能描述:8位微控制器 -MCU RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數據總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數據 RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
| COP8SGE728M8/63SN | 功能描述:8位微控制器 -MCU RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數據總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數據 RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
| COP8SGE728M8/NOPB | 功能描述:8位微控制器 -MCU RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數據總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數據 RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
| COP8SGE728N8 | 功能描述:8位微控制器 -MCU RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數據總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數據 RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
發(fā)布緊急采購，3分鐘左右您將得到回復。