參數(shù)資料
    型號(hào)： COP8SGB044Q3
    廠商： National Semiconductor Corporation
    英文描述： LMK03002 / LMK03002C Precision Clock Conditioner with Integrated VCO
    中文描述： 8位的CMOS基于ROM和OTP微控制器具有8K到32K的內(nèi)存，2個(gè)比較器和USART
    文件頁(yè)數(shù)： 19/62頁(yè)
    文件大小： 913K
    代理商： COP8SGB044Q3
    5.0 Functional Description
    (Continued)
    The device comes out of reset with both the WATCH-
    DOG logic and the Clock Monitor detector armed, with the
    WATCHDOG service window bits set and the Clock Monitor
    bit set. The WATCHDOG and Clock Monitor circuits are
    inhibited during reset. The WATCHDOG service window bits
    being initialized high default to the maximum WATCHDOG
    service window of 64k t
    clock cycles. The Clock Monitor bit
    being initialized high will cause a Clock Monitor error follow-
    ing reset if the clock has not reached the minimum specified
    frequency at the termination of reset. A Clock Monitor error
    will cause an active low error output on pin G1. This error
    output will continue until 16 t
    –32 t
    clock cycles following
    the clock frequency reaching the minimum specified value,
    at which time the G1 output will go high.
    5.9.1 External Reset
    The RESET input when pulled low initializes the device. The
    RESET pin must be held low for a minimum of one instruc-
    tion cycle to guarantee a valid reset. During Power-Up ini-
    tialization, the user must ensure that the RESET pin is held
    low until the device is within the specified V
    CC
    voltage. An
    R/C circuit on the RESET pin with a delay 5 times (5x)
    greater than the power supply rise time or 15 μs whichever is
    greater, is recommended. Reset should also be wide enough
    to ensure crystal start-up upon Power-Up.
    RESET may also be used to cause an exit from the HALT
    mode.
    A recommended reset circuit for this device is shown in
    Figure 9
    5.9.2 On-Chip Power-On Reset
    The on-chip reset circuit is selected by a bit in the ECON
    register. When enabled, the device generates an internal
    reset as V
    rises to a voltage level above 2.0V. The on-chip
    reset circuitry is able to detect both fast and slow rise times
    on V
    (V
    rise time between 10 ns and 50 ms).To guar-
    antee an on-chip power-on-reset, V
    must start at a voltage
    less than the start voltage specified in the DC characteris-
    tics. Also, if V
    be lowered to the start voltage before
    powering back up to the operating range. If this is not pos-
    sible, it is recommended that external reset be used.
    Under no circumstances should the RESET pin be allowed
    to float. If the on-chip Power-On Reset feature is being used,
    RESET pin should be connected directly, or through a
    pull-up resistor, to V
    CC
    . The output of the power-on reset
    detector will
    always
    preset the Idle timer to 0FFF(4096 t
    C
    ).
    At this time, the internal reset will be generated.
    If the Power-On Reset feature is enabled, the internal reset
    will not be turned off until the Idle timer underflows. The
    internal reset will perform the same functions as external
    reset. The user is responsible for ensuring that V
    is at the
    minimum level for the operating frequency within the 4096
    t
    . After the underflow, the logic is designed such that no
    additional internal resets occur as long as V
    CC
    remains
    above 2.0V.
    The contents of data registers and RAM are unknown fol-
    lowing the on-chip reset.
    10131714
    RC
    >
    5x power supply rise time or 15 μs, whichever is greater.
    FIGURE 9. Reset Circuit Using External Reset
    10131715
    FIGURE 10. Reset Timing (Power-On Reset Enabled)
    with V
    CC
    Tied to RESET
    10131716
    FIGURE 11. Reset Circuit Using Power-On Reset
    C
    www.national.com
    19
    相關(guān)PDF資料
    PDF描述
    COP8SGB044Q6 LMK03002 / LMK03002C Precision Clock Conditioner with Integrated VCO; Package: LLP; No of Pins: 48
    COP8SGB044Q7 LMK03002 / LMK03002C Precision Clock Conditioner with Integrated VCO; Package: LLP; No of Pins: 48
    COP8SGB044Q8 LMK03002 / LMK03002C Precision Clock Conditioner with Integrated VCO; Package: LLP; No of Pins: 48
    COP8SGB044Q9 LMK03002 / LMK03002C Precision Clock Conditioner with Integrated VCO; Package: LLP; No of Pins: 48
    COP8SGB044V3 LMK03000 Family Precision Clock Conditioner with Integrated VCO
    相關(guān)代理商/技術(shù)參數(shù)
    參數(shù)描述
    COP8SGB044Q6 制造商:NSC 制造商全稱(chēng):National Semiconductor 功能描述:8-Bit CMOS ROM Based and OTP Microcontrollers with 8k to 32k Memory, Two Comparators and USART
    COP8SGB044Q7 制造商:NSC 制造商全稱(chēng):National Semiconductor 功能描述:8-Bit CMOS ROM Based and OTP Microcontrollers with 8k to 32k Memory, Two Comparators and USART
    COP8SGB044Q8 制造商:NSC 制造商全稱(chēng):National Semiconductor 功能描述:8-Bit CMOS ROM Based and OTP Microcontrollers with 8k to 32k Memory, Two Comparators and USART
    COP8SGB044Q9 制造商:NSC 制造商全稱(chēng):National Semiconductor 功能描述:8-Bit CMOS ROM Based and OTP Microcontrollers with 8k to 32k Memory, Two Comparators and USART
    COP8SGB044V3 制造商:NSC 制造商全稱(chēng):National Semiconductor 功能描述:8-Bit CMOS ROM Based and OTP Microcontrollers with 8k to 32k Memory, Two Comparators and USART
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