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參數(shù)資料
| 型號： | COP8SGB040N3 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | LMH7324 Quad 700 ps High Speed Comparator with RSPECL Outputs |
| 中文描述： | 8位的CMOS基于ROM和OTP微控制器具有8K到32K的內(nèi)存，2個(gè)比較器和USART |
| 文件頁數(shù)： | 28/62頁 |
| 文件大小： | 913K |
| 代理商： | COP8SGB040N3 |
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8.0 USART
Each device contains a full-duplex software programmable
USART. The USART (Figure 21) consists of a transmit shift
register, a receive shift register and seven addressable reg-
isters, as follows: a transmit buffer register (TBUF), a re-
ceiver buffer register (RBUF), a USART control and status
register (ENU), a USART receive control and status register
(ENUR), a USART interrupt and clock source register
(ENUI), a prescaler select register (PSR) and baud (BAUD)
register. The ENU register contains flags for transmit and
receive functions; this register also determines the length of
the data frame (7, 8 or 9 bits), the value of the ninth bit in
transmission, and parity selection bits. The ENUR register
flags framing, data overrun and parity errors while the US-
ART is receiving.
Other functions of the ENUR register include saving the
ninth bit received in the data frame, enabling or disabling the
USART’s attention mode of operation and providing addi-
tional receiver/transmitter status information via RCVG and
XMTG bits. The determination of an internal or external clock
source is done by the ENUI register, as well as selecting the
number of stop bits and enabling or disabling transmit and
receive interrupts. A control flag in this register can also
select the USART mode of operation: asynchronous or
synchronous.
8.1 USART CONTROL AND STATUS REGISTERS
The operation of the USART is programmed through three
registers: ENU, ENUR and ENUI.
8.2 DESCRIPTION OF USART REGISTER BITS
ENU-USART Control and Status Register (Address at 0BA)
PEN
PSEL1 XBIT9/
CHL1
CHL0
ERR
RBFL
TBMT
PSEL0
Bit 7
Bit 0
10131739
FIGURE 21. USART Block Diagram
C
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PDF描述 |
|---|---|
| COP8SGB040N6 | LMH7324 Quad 700 ps High Speed Comparator with RSPECL Outputs; Package: LLP; No of Pins: 32 |
| COP8SGB040N7 | LMH7324 Quad 700 ps High Speed Comparator with RSPECL Outputs; Package: LLP; No of Pins: 32 |
| COP8SGB040N8 | LMK01000 / LMK01010 / LMK01020 1.6 GHz High Performance Clock Buffer, Divider, and Distributor |
| COP8SGB040N9 | LMK01000 / LMK01010 / LMK01020 1.6 GHz High Performance Clock Buffer, Divider, and Distributor; Package: LLP; No of Pins: 48 |
| COP8SGB040Q3 | LMK01000 / LMK01010 / LMK01020 1.6 GHz High Performance Clock Buffer, Divider, and Distributor; Package: LLP; No of Pins: 48 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| COP8SGB040N6 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:8-Bit CMOS ROM Based and OTP Microcontrollers with 8k to 32k Memory, Two Comparators and USART |
| COP8SGB040N7 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:8-Bit CMOS ROM Based and OTP Microcontrollers with 8k to 32k Memory, Two Comparators and USART |
| COP8SGB040N8 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:8-Bit CMOS ROM Based and OTP Microcontrollers with 8k to 32k Memory, Two Comparators and USART |
| COP8SGB040N9 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:8-Bit CMOS ROM Based and OTP Microcontrollers with 8k to 32k Memory, Two Comparators and USART |
| COP8SGB040Q3 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:8-Bit CMOS ROM Based and OTP Microcontrollers with 8k to 32k Memory, Two Comparators and USART |
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