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  • 參數(shù)資料
    型號: COP8SGA640V6
    廠商: National Semiconductor Corporation
    英文描述: LMH6560 Quad, High-Speed, Closed-Loop Buffer; Package: TSSOP; No of Pins: 14
    中文描述: 8位的CMOS基于ROM和OTP微控制器具有8K到32K的內(nèi)存,2個(gè)比較器和USART
    文件頁數(shù): 44/62頁
    文件大?。?/td> 913K
    代理商: COP8SGA640V6
    12.0 MICROWIRE/PLUS
    (Continued)
    12.1.2 MICROWIRE/PLUS Slave Mode Operation
    In the MICROWIRE/PLUS Slave mode of operation the SK
    clock is generated by an external source. Setting the MSEL
    bit in the CNTRL register enables the SO and SK functions
    onto the G Port. The SK pin must be selected as an input
    and the SO pin is selected as an output pin by setting and
    resetting the appropriate bits in the Port G configuration
    register. Table 11 summarizes the settings required to enter
    the Slave mode of operation.
    TABLE 11. MICROWIRE/PLUS Mode Settings
    This table assumes that the control flag MSEL is set.
    G4 (SO)
    Config. Bit
    1
    G5 (SK)
    Config. Bit
    1
    G4
    Fun.
    SO
    G5
    Fun.
    Int.
    SK
    Int.
    SK
    Ext.
    SK
    Ext.
    SK
    Operation
    MICROWIRE/PLUS
    Master
    MICROWIRE/PLUS
    Master
    MICROWIRE/PLUS
    Slave
    MICROWIRE/PLUS
    Slave
    0
    1
    TRI-
    STATE
    SO
    1
    0
    0
    0
    TRI-
    STATE
    The user must set the BUSY flag immediately upon entering
    the Slave mode. This ensures that all data bits sent by the
    Master is shifted properly. After eight clock pulses the BUSY
    flag is clear, the shift clock is stopped, and the sequence
    may be repeated.
    12.1.3 Alternate SK Phase Operation and SK Idle P
    The device allows either the normal SK clock or an alternate
    phase SK clock to shift data in and out of the SIO register. In
    both the modes the SK idle polarity can be either high or low.
    The polarity is selected by bit 5 of Port G data register. In the
    normal mode data is shifted in on the rising edge of the SK
    clock and the data is shifted out on the falling edge of the SK
    clock. In the alternate SK phase operation, data is shifted in
    on the falling edge of the SK clock and shifted out on the
    rising edge of the SK clock. Bit 6 of Port G configuration
    register selects the SK edge.
    A control flag, SKSEL, allows either the normal SK clock or
    the alternate SK clock to be selected. Resetting SKSEL
    causes the MICROWIRE/PLUS logic to be clocked from the
    normal SK signal. Setting the SKSEL flag selects the alter-
    nate SK clock. The SKSEL is mapped into the G6 configu-
    ration bit. The SKSEL flag will power up in the reset condi-
    tion, selecting the normal SK signal.
    TABLE 12. MICROWIRE/PLUS Shift Clock Polarity and Sample/Shift Phase
    Port G
    SK Phase
    G6 (SKSEL)
    Config. Bit
    0
    1
    0
    1
    G5 Data
    Bit
    0
    0
    1
    1
    SO Clocked Out On:
    SI Sampled On:
    SK Idle
    Phase
    Normal
    Alternate
    Alternate
    Normal
    SK Falling Edge
    SK Rising Edge
    SK Rising Edge
    SK Falling Edge
    SK Rising Edge
    SK Falling Edge
    SK Falling Edge
    SK Rising Edge
    Low
    Low
    High
    High
    10131733
    FIGURE 29. MICROWIRE/PLUS SPI Mode Interface Timing, Normal SK Mode, SK Idle Phase being Low
    C
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    相關(guān)代理商/技術(shù)參數(shù)
    參數(shù)描述
    COP8SGA640V7 制造商:NSC 制造商全稱:National Semiconductor 功能描述:8-Bit CMOS ROM Based and OTP Microcontrollers with 8k to 32k Memory, Two Comparators and USART
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    COP8SGA640V9 制造商:NSC 制造商全稱:National Semiconductor 功能描述:8-Bit CMOS ROM Based and OTP Microcontrollers with 8k to 32k Memory, Two Comparators and USART
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    COP8SGA644D6 制造商:NSC 制造商全稱:National Semiconductor 功能描述:8-Bit CMOS ROM Based and OTP Microcontrollers with 8k to 32k Memory, Two Comparators and USART