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    • 您現(xiàn)在的位置:買賣IC網(wǎng) > PDF目錄379950 > COP8SGA640Q6 (National Semiconductor Corporation) LMH6559 High-Speed, Closed-Loop Buffer; Package: SOT-23; No of Pins: 5 PDF資料下載
    參數(shù)資料
    型號: COP8SGA640Q6
    廠商: National Semiconductor Corporation
    英文描述: LMH6559 High-Speed, Closed-Loop Buffer; Package: SOT-23; No of Pins: 5
    中文描述: 8位的CMOS基于ROM和OTP微控制器具有8K到32K的內(nèi)存,2個比較器和USART
    文件頁數(shù): 16/62頁
    文件大小: 913K
    代理商: COP8SGA640Q6
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    5.0 Functional Description
    The architecture of the devices are a modified Harvard ar-
    chitecture. With the Harvard architecture, the program
    memory ROM is separated from the data store memory
    (RAM). Both ROM and RAM have their own separate ad-
    dressing space with separate address buses. The architec-
    ture, though based on the Harvard architecture, permits
    transfer of data from ROM to RAM.
    5.1 CPU REGISTERS
    The CPU can do an 8-bit addition, subtraction, logical or shift
    operation in one instruction (t
    C
    ) cycle time.
    There are six CPU registers:
    A is the 8-bit Accumulator Register
    PC is the 15-bit Program Counter Register
    PU is the upper 7 bits of the program counter (PC)
    PL is the lower 8 bits of the program counter (PC)
    B is an 8-bit RAM address pointer, which can be optionally
    post auto incremented or decremented.
    X is an 8-bit alternate RAM address pointer, which can be
    optionally post auto incremented or decremented.
    S is the 8-bit Segment Address Register used to extend the
    lower half of the address range (00 to 7F) into 256 data
    segments of 128 bytes each.
    SP is the 8-bit stack pointer, which points to the subroutine/
    interrupt stack (in RAM). With reset the SP is initialized to
    RAM address 02F Hex (devices with 64 bytes of RAM), or
    initialized to RAM address 06F Hex (devices with 128 bytes
    of RAM).
    All the CPU registers are memory mapped with the excep-
    tion of the Accumulator (A) and the Program Counter (PC).
    5.2 PROGRAM MEMORY
    The program memory consists of varies sizes of ROM.
    These bytes may hold program instructions or constant data
    (data tables for the LAID instruction, jump vectors for the JID
    instruction, and interrupt vectors for the VIS instruction). The
    program memory is addressed by the 15-bit program
    counter (PC). All interrupts in the device vector to program
    memory location 0FF Hex. The contents of the program
    memory read 00 Hex in the erased state. Program execution
    starts at location 0 after RESET.
    5.3 DATA MEMORY
    The data memory address space includes the on-chip RAM
    and data registers, the I/O registers (Configuration, Data and
    Pin), the control registers, the MICROWIRE/PLUS SIO shift
    register, and the various registers, and counters associated
    with the timers (with the exception of the IDLE timer). Data
    memory is addressed directly by the instruction or indirectly
    by the B, X and SP pointers.
    The data memory consists of 256 or 512 bytes of RAM.
    Sixteen bytes of RAM are mapped as “registers” at ad-
    dresses 0F0 to 0FE Hex. These registers can be loaded
    immediately, and also decremented and tested with the
    DRSZ (decrement register and skip if zero) instruction. The
    memory pointer registers X, SP and B are memory mapped
    into this space at address locations 0FC to 0FE Hex respec-
    tively, with the other registers (except 0FF) being available
    for general usage.
    The instruction set permits any bit in memory to be set, reset
    or tested. All I/O and registers (except A and PC) are
    memory mapped; therefore, I/O bits and register bits can be
    directly and individually set, reset and tested. The accumu-
    lator (A) bits can also be directly and individually tested.
    Note:
    RAM contents are undefined upon power-up.
    5.4 DATA MEMORY SEGMENT RAM EXTENSION
    Data memory address 0FF is used as a memory mapped
    location for the Data Segment Address Register (S).
    The data store memory is either addressed directly by a
    single byte address within the instruction, or indirectly rela-
    tive to the reference of the B, X, or SP pointers (each
    contains a single-byte address). This single-byte address
    allows an addressing range of 256 locations from 00 to FF
    hex. The upper bit of this single-byte address divides the
    data store memory into two separate sections as outlined
    previously. With the exception of the RAM register memory
    from address locations 00F0 to 00FF, all RAM memory is
    memory mapped with the upper bit of the single-byte ad-
    dress being equal to zero. This allows the upper bit of the
    single-byte address to determine whether or not the base
    address range (from 0000 to 00FF) is extended. If this upper
    bit equals one (representing address range 0080 to 00FF),
    then address extension does not take place. Alternatively, if
    this upper bit equals zero, then the data segment extension
    register S is used to extend the base address range (from
    0000 to 007F) from XX00 to XX7F, where XX represents the
    8 bits from the S register. Thus the 128-byte data segment
    extensions are located from addresses 0100 to 017F for
    data segment 1, 0200 to 027F for data segment 2, etc., up to
    FF00 to FF7F for data segment 255. The base address
    range from 0000 to 007F represents data segment 0.
    Figure 7 illustrates how the S register data memory exten-
    sion is used in extending the lower half of the base address
    range (00 to 7F hex) into 256 data segments of 128 bytes
    each, with a total addressing range of 32 kbytes from XX00
    to XX7F. This organization allows a total of 256 data seg-
    ments of 128 bytes each with an additional upper base
    segment of 128 bytes. Furthermore, all addressing modes
    are available for all data segments. The S register must be
    changed under program control to move from one data
    segment (128 bytes) to another. However, the upper base
    segment (containing the 16 memory registers, I/O registers,
    control registers, etc.) is always available regardless of the
    contents of the S register, since the upper base segment
    (address range 0080 to 00FF) is independent of data seg-
    ment extension.
    C
    www.national.com
    16
    相關(guān)PDF資料
    PDF描述
    COP8SGA640Q7 LMH6559 High-Speed, Closed-Loop Buffer; Package: SOT-23; No of Pins: 5
    COP8SGA640Q8 LMH6560 Quad, High-Speed, Closed-Loop Buffer; Package: SOIC NARROW; No of Pins: 14
    COP8SGA640Q9 LMH6560 Quad, High-Speed, Closed-Loop Buffer; Package: SOIC NARROW; No of Pins: 14
    COP8SGA640V3 LMH6560 Quad, High-Speed, Closed-Loop Buffer; Package: TSSOP; No of Pins: 14
    COP8SGA640V6 LMH6560 Quad, High-Speed, Closed-Loop Buffer; Package: TSSOP; No of Pins: 14
    相關(guān)代理商/技術(shù)參數(shù)
    參數(shù)描述
    COP8SGA640Q7 制造商:NSC 制造商全稱:National Semiconductor 功能描述:8-Bit CMOS ROM Based and OTP Microcontrollers with 8k to 32k Memory, Two Comparators and USART
    COP8SGA640Q8 制造商:NSC 制造商全稱:National Semiconductor 功能描述:8-Bit CMOS ROM Based and OTP Microcontrollers with 8k to 32k Memory, Two Comparators and USART
    COP8SGA640Q9 制造商:NSC 制造商全稱:National Semiconductor 功能描述:8-Bit CMOS ROM Based and OTP Microcontrollers with 8k to 32k Memory, Two Comparators and USART
    COP8SGA640V3 制造商:NSC 制造商全稱:National Semiconductor 功能描述:8-Bit CMOS ROM Based and OTP Microcontrollers with 8k to 32k Memory, Two Comparators and USART
    COP8SGA640V6 制造商:NSC 制造商全稱:National Semiconductor 功能描述:8-Bit CMOS ROM Based and OTP Microcontrollers with 8k to 32k Memory, Two Comparators and USART
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