參數(shù)資料
型號： COP8CCR9LVA7/NOPB
廠商： National Semiconductor
文件頁數(shù)： 41/111頁
文件大?。?/td> 0K
描述： MCU 8BIT FLASH 32K MEM 68-PLCC
標(biāo)準(zhǔn)包裝： 18
系列： COP8™ 8C
核心處理器： COP8
芯體尺寸： 8-位
速度： 20MHz
連通性： Microwire/Plus（SPI），UART/USART
外圍設(shè)備： 欠壓檢測/復(fù)位，POR，PWM，WDT
輸入/輸出數(shù)： 59
程序存儲器容量： 32KB（32K x 8）
程序存儲器類型： 閃存
RAM 容量： 1K x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 16x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 125°C
封裝/外殼： 68-LCC（J 形引線）
包裝： 管件
其它名稱： COP8CCR9LVA7
SNOS535I – OCTOBER 2000 – REVISED MARCH 2013
As described in Option Register, there is a bit, FLEX, that controls whether the device exits RESET
executing from the flash memory or the Boot ROM. The user must program the FLEX bit as appropriate
for the application. In the erased state, the FLEX bit = 0 and the device will power-up executing from Boot
ROM. When FLEX = 0, this assumes that either the MICROWIRE/PLUS ISP routine or external
programming is being used to program the device. If using the MICROWIRE/PLUS ISP routine, the
software in the boot ROM will monitor the MICROWIRE/PLUS for commands to program the flash
memory. When programming the flash program memory is complete, the FLEX bit will have to be
programmed to a 1 and the device will have to be reset, either by pulling external Reset to ground or by a
MICROWIRE/PLUS ISP EXIT command, before execution from flash program memory will occur.
If FLEX = 1, upon exiting Reset, the device will begin executing from location 0000 in the flash program
memory. The assumption, here, is that either the application is not using ISP, is using MICROWIRE/PLUS
ISP by jumping to it within the application code, or is using a customized ISP routine. If a customized ISP
routine is being used, then it must be programmed into the flash memory by means of the
MICROWIRE/PLUS ISP or external programming as described in the preceding paragraph.
5.10.3 REGISTERS
There are six registers required to support ISP: Address Register Hi byte (ISPADHI), Address Register
Low byte (ISPADLO), Read Data Register (ISPRD), Write Data Register (ISPWR), Write Timing Register
(PGMTIM), and the Control Register (ISPCNTRL). The ISPCNTRL Register is not available to the user.
5.10.3.1 ISP Address Registers
The address registers (ISPADHI & ISPADLO) are used to specify the address of the byte of data being
written or read. For page erase operations, the address of the beginning of the page should be loaded.
For mass erase operations, 0000 must be placed into the address registers. When reading the Option
register, FFFF (hex) should be placed into the address registers. Registers ISPADHI and ISPADLO are
cleared to 00 on Reset. These registers can be loaded from either flash program memory or Boot ROM
and must be maintained for the entire duration of the operation.
NOTE
The actual memory address of the Option Register is 7FFF (hex), however the
MICROWIRE/PLUS ISP routines require the address FFFF (hex) to be used to read the
Option Register when the Flash Memory is secured.
Table 5-3. High Byte of ISP Address
ISPADHi
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Addr 15
Addr 14
Addr 13
Addr 12
Addr 11
Addr 10
Addr 9
Addr 8
Table 5-4. Low Byte of ISP AddressThis table assumes that the control flag
MSEL is set.
ISPADLO
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Addr 7
Addr 6
Addr 5
Addr 4
Addr 3
Addr 2
Addr 1
Addr 0
5.10.3.2 ISP Read Data Register
The Read Data Register (ISPRD) contains the value read back from a read operation. This register can be
accessed from either flash program memory or Boot ROM. This register is undefined on Reset.
Copyright 2000–2013, Texas Instruments Incorporated
Functional Description
35
Product Folder Links: COP8CBR9 COP8CCR9 COP8CDR9
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