參數(shù)資料
型號(hào)： COP8CBR9HVA8/NOPB
廠商： National Semiconductor
文件頁(yè)數(shù)： 88/111頁(yè)
文件大?。?/td> 0K
描述： IC MCU EEPROM 8BIT 32K 44PLCC
標(biāo)準(zhǔn)包裝： 25
系列： COP8™ 8C
核心處理器： COP8
芯體尺寸： 8-位
速度： 20MHz
連通性： Microwire/Plus（SPI），UART/USART
外圍設(shè)備： 欠壓檢測(cè)/復(fù)位，POR，PWM，WDT
輸入/輸出數(shù)： 37
程序存儲(chǔ)器容量： 32KB（32K x 8）
程序存儲(chǔ)器類(lèi)型： 閃存
RAM 容量： 1K x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 16x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 44-LCC（J 形引線(xiàn)）
包裝： 管件
其它名稱(chēng)： *COP8CBR9HVA8
*COP8CBR9HVA8/NOPB
COP8CBR9HVA8
SNOS535I – OCTOBER 2000 – REVISED MARCH 2013
Figure 5-24. VIS Operation
5.15.4 NON-MASKABLE INTERRUPT
5.15.4.1 Pending Flag
There is a pending flag bit associated with the non-maskable Software Trap interrupt, called STPND. This
pending flag is not memory-mapped and cannot be accessed directly by the software.
The pending flag is reset to zero when a device Reset occurs. When the non-maskable interrupt occurs,
the associated pending bit is set to 1. The interrupt service routine should contain an RPND instruction to
reset the pending flag to zero. The RPND instruction always resets the STPND flag.
5.15.4.2 Software Trap
The Software Trap is a special kind of non-maskable interrupt which occurs when the INTR instruction
(used to acknowledge interrupts) is fetched from program memory and placed in the instruction register.
This can happen in a variety of ways, usually because of an error condition. Some examples of causes
are listed below.
If the program counter incorrectly points to a memory location beyond the programmed Flash memory
space, the unused memory location returns zeros which is interpreted as the INTR instruction.
If the stack is popped beyond the allowed limit (address 06F Hex), a 7FFF will be loaded into the PC.
Since the Option Register resides at this location, and to maintain the integrity of the stack overpop
protection, the Flash memory will return a zero on an instruction fetch and a software trap will be
triggered.
A Software Trap can be triggered by a temporary hardware condition such as a brownout or power supply
glitch.
The Software Trap has the highest priority of all interrupts. When a Software Trap occurs, the STPND bit
is set. The GIE bit is not affected and the pending bit (not accessible by the user) is used to inhibit other
interrupts and to direct the program to the ST service routine with the VIS instruction. Nothing can interrupt
a Software Trap service routine except for another Software Trap. The STPND can be reset only by the
RPND instruction or a chip Reset.
78
Functional Description
Copyright 2000–2013, Texas Instruments Incorporated
Product Folder Links: COP8CBR9 COP8CCR9 COP8CDR9
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