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參數(shù)資料
| 型號： | COP413C |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Single-Chip CMOS Microcontrollers |
| 中文描述： | 單芯片的CMOS微控制器 |
| 文件頁數(shù)： | 7/16頁 |
| 文件大?。?/td> | 223K |
| 代理商： | COP413C |
Functional Description
To ease reading of this description, only COP413C is refer-
enced; however, all such references apply equally to
COP413CH, COP313C, and COP313CH.
A block diagram of the COP413C is given in Figure 1. Data
paths are illustrated in simplified form to depict how the vari-
ous logic elements communicate with each other in imple-
menting the instruction set of the device. Positive logic is
used. When a bit is set, it is a logic ‘‘1’’; when a bit is reset, it
is a logic ‘‘0’’.
PROGRAM MEMORY
Program memory consists of a 512-byte ROM. As can be
seen by an examination of the COP413C instruction set,
these words may be program instructions, program data, or
ROM addressing data. Because of the special characteris-
tics associated with the JP, JSRP, JID, and LQID instruc-
tions, ROM must often be thought of as being organized into
8 pages of 64 words (bytes) each.
ROM ADDRESSING
ROM addressing is accomplished by a 9-bit PC register. Its
binary value selects one of the 512 8-bit words contained in
ROM. A new address is loaded into the PC register during
each instruction cycle. Unless the instruction is a transfer of
control instruction, the PC register is loaded with the next
sequential 9-bit binary count value. Two levels of subroutine
nesting are implemented by two 9-bit subroutine save regis-
ters, SA and SB.
ROM instruction words are fetched, decoded, and executed
by the instruction decode, control and skip logic circuitry.
DATA MEMORY
Data Memory consists of a 128-bit RAM, organized as four
data registers of 8
c
4-bit digits. RAM addressing is imple-
mented by a 6-bit B register whose upper two bits (Br) se-
lects one of four data registers and lower three bits of the 4-
bit Bd select one of eight 4-bit digits in the selected data
register. While the 4-bit contents of the selected RAM digit
(M) are usually loaded into or from, or exchanged with, the A
register (accumulator), they may also be loaded into the Q
latches or loaded from the L ports. RAM addressing may
also be performed directly by the XAD 3, 15 instruction.
The most significant bit of Bd is not used to select a RAM
digit. Hence, each physical digit of RAM may be selected by
two different values of Bd as shown in Figure 4. The skip
condition for XIS and XDS instructions will be true if Bd
changes between 0 to 15, but not between 7 and 8 (see
Table III).
INTERNAL LOGIC
The internal logic of the COP413C is designed to ensure
fully static operation of the device.
The 4-bit A register (accumulator) is the source and destina-
tion register for most I/O, arithmetic, logic and data memory
access operations. It can also be used to load the Bd por-
tion of the B register, to load four bits of the 8-bit Q latch
data and to perform data exchanges with the SIO register.
The 4-bit adder performs the arithmetic and logic functions
of the COP413C, storing its results in A. It also outputs the
carry information to a 1-bit carry register, most often em-
ployed to indicate arithmetic overflow. The C register, in
conjunction with the XAS instruction and the EN register,
also serves to control the SK output. C can be outputted
directly to SK or can enable SK to be a sync clock each
instruction cycle time. (See XAS instruction and EN register
description below.)
The G register contents are outputs to four general purpose
bidirectional I/O ports.
The Q register is an internal, latched, 8-bit register, used to
hold data loaded from RAM and A, as well as 8-bit data from
ROM. Its contents are output to the L I/O ports when the L
drivers are enabled under program control. (See LEI instruc-
tion.)
The eight L drivers, when enabled, output the contents of
latched Q data to the L I/O ports. Also, the contents of L
may be read directly into A and RAM.
*
Can be directly addressed by
LBI instruction (See Table 3)
TL/DD/8537–4
FIGURE 4. RAM Digit Address to Physical
RAM Digit Mapping
7
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| COP413CH | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Single-Chip CMOS Microcontrollers |
| COP413CH-XXX/D | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:4-Bit Microcontroller |
| COP413CH-XXX/N | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:4-Bit Microcontroller |
| COP413C-XXX/D | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:4-Bit Microcontroller |
| COP413C-XXX/N | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:4-Bit Microcontroller |
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