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| 型號(hào)： | CM9 |
| 英文描述： | Mixed-Signal CMOS and specialized analog processes |
| 中文描述： | 混合信號(hào)CMOS工藝和專門模擬 |
| 文件頁數(shù)： | 1/1頁 |
| 文件大?。?/td> | 33K |
| 代理商： | CM9 |
Table 1:
9 μm
Units
Metal pitch (width/space)
8 / 5
μ
m
Contact
8 x 8
μ
m
Gate geometry
9
μ
m
P-well junction depth
9
μ
m
N+ junction depth
2.4
μ
m
P+ junction depth
2.6
μ
m
Gate oxide thickness
1050
9 MICRON - 15 volts
Units
Conditions
N Channel
min. typ. max.
P Channel
min. typ. max.
Vt (50 x 9
μ
m)
1.0
1.3
1.6
1.6
1.9
2.2
V
saturation
Ids (50 x 9
μ
m)
200
60
μA/μm
Vds=Vgs=3v
Gain
β
(50 x 9
μ
m)
700
200
μA/V
2
Bvdss
20
28
20
30
V
Ids=1μA
Field threshold
23
20
V
Ids=1μA
L effective
5.2
4.8
μm
L drawn =
9μm
MOSFET Electrical Parameters
9 MICRON -15 volts
min. typ. max.
Pwell
1500
N+
35
45
55
P+
40
70
100
Metal I
0.038
Resistances (
/sq.)
Features
Metal Gate Process
13 μm Metal Pitch
16 Volts Maximum Operating Voltage
Simple Process (7 masks)
Very Short Cycle Time
Very High Yield
Description
The
9 μ
m process is a CMOS process with an operating voltage
range from 5 to 16 volts. The gate material is metal; which is
common in many mature designs. An advantage of this process
is its simplicity and its short cycle time.
9 Micron Metal Gate
CMOS Process
Process parameters
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