參數(shù)資料
型號(hào)： CLC432AJE-TR13
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： 運(yùn)算放大器
英文描述： DUAL OP-AMP, 7000 uV OFFSET-MAX, 92 MHz BAND WIDTH, PDSO8
封裝： PLASTIC, SOIC-8
文件頁(yè)數(shù)： 27/27頁(yè)
文件大?。?/td> 685K
代理商： CLC432AJE-TR13
Typical Performance Characteristics (T
A = +25C, AV = +2, VCC = ±15V, unless
specified) (Continued)
Application Division
Introduction
The
CLC431
and
the
CLC432
are
dual
wideband
current-feedback op amps that operate from single (+10V to
+33V) or dual (±5V to ±16.5) power supplies. The CLC431
is equipped with a disable feature and is offered in 14-dip
DIP and SOIC packages. The CLC432 is packaged in a
standard 8-pin dual pinout and is offered in an 8-pin DIP and
SOIC. Evaluation boards are available for each version of
both devices. The evaluation boards can assist in the device
and/or application evaluation and were used to generate the
typical device performance plots on the preceding pages.
Each of the CLC431/CLC432’s dual channels provide
closely matched DC & AC electrical performance character-
istics making them ideal choices for wideband signal pro-
cessing. The CLC431, with its disable features, can easily be
configured as a 2:1 mux or several can be used to form a
10:1 mux without performance degradation. The two
closely-matched channels of the CLC432 can be combined
to form composite circuits for such applications as filter
blocks, integrators, transimpedance amplifiers and differen-
tial line drives and receivers.
Feedback Resistor Selection
The
loop
gain
and
frequency
response
for
a
current-feedback operational amplifier is determined largely
by the feedback resistor (R
f). Package parasitic also influ-
ence ac response. Since the package parasitics of the
CLC431 and the CLC4332 are different, the optimum fre-
quency and phase response are obtained with different val-
ues of feedback resistor (for A
V= +2; CLC431: Rf = 866,
CLC432: R
f
= 750
). The Electrical Characteristics and
Typical Performance plot are valid for both devices under the
specified conditions. Generally, lowering R
f from its recom-
mended value will peak the frequency response and ex-
tended the bandwidth while increasing its value will roll off
the response. Reducing the value of R
f too far below its
recommended value will cause overshoot, ringing and even-
tually oscillation. For more information see Application Note
OA-20 and OA-13.
In order to minimize the devices’ frequency and phase re-
sponse for gains other than +2V/V it is recommended to
adjust the value of the feedback resistor. The two plots found
in the Typical Performance section entitled “Recommended
R
f
vs.
Gain”
provide
the
means
of
selecting
the
feedback-resistor value that optimizes frequency and phase
response over the CLC431/CLC432’s gain range. Both pots
show the value of R
f approaching a nonzero minimum at
high
non-inverting
gains,
which
is
characteristic
of
current-feedback op amps and yields best results. The linear
portion of the two R
f vs. Inverting-gain curves results from
the limitation placed on R
g (i.e. Rg ≥ 50) in order to main-
tain an adequate input impedance for the inverting configu-
ration. It should be noted that for stable operation a
non-inverting gain of +1 requires an R
f equal to 1k for both
the CLC431 and the CLC4332.
CLC431 Disable Feature
The CLC431 disable feature can be operated either
single-endedly or differentially thereby accommodating a
wide range of logic families. There are three pins associated
with the disable feature of each of the CLC431’s two ampli-
fiers: DIS,DIS and V
RTTL (please see pinout on front page).
Also note that both amplifiers are guaranteed to be enabled
if all three of these pins are unconnected.
Figure 1 illustrates the single-ended mode of the CLC431’s
disable feature for logic families such as TTL and CMOS. In
order to operate properly, V
RTTL must be grounded, thereby
biasing DIS to approximately +1.4V through the two internal
series diodes. For single-ended operation, DIS should be left
floating. Applying a TTL or CMOS logic “high” (i.e.>2.0Volts)
to DIS will switch the tail current of the differential pair to Q1
and “shut down” Q2 which results in the disabling of that
channel of the CLC431. Alternatively, applying a logic “l(fā)ow”
(i.e. <0.8Volts) to DIS will switch the tail current from Q1 to
Q2 effectively enabling that channel. If DIS is left floating
under single-ended operation, then the associated amplifier
is guaranteed to be disabled.
Recommended R
fvs. VCC (AV = +2)
DS012712-26
CLC431/432
www.national.com
9
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