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參數(shù)資料
| 型號(hào)： | CL10K50SFC256-1X |
| 英文描述： | FPGA |
| 中文描述： | FPGA的 |
| 文件頁數(shù)： | 6/16頁 |
| 文件大小： | 178K |
| 代理商： | CL10K50SFC256-1X |
LIBERATOR CL10K30A
Page 14
AC Electrical Specifications cont.
External Bi-Directional Timing Parameters[5]
Symbol
Parameter
Min
Max
Min
Max
Min
Max Unit
tINSUBIDIR
Setup for Bi-directional Pins with Global
Clock at Adjacent LE Registers
4.2
4.9
6.8
ns
tINHBIDIR
Hold Time for Bi-directional Pins with Global
Glock at Adjacent LE Registers
0.0
ns
tOUTCOBIDIR
Clock-to-output Delay for Bi-directional Pins
with Global Clock at IOE Register
2.0
5.4
2.0
6.2
2.0
8.3
ns
tXZBIDIR
Synchronous IOE Output Buffer Disable
Delay
6.2
7.5
9.8
ns
tZXBIDIR
Synchronous IOE Output Buffer Disable
Delay, Slow Slew Rate = off
6.2
7.5
9.8
ns
Speed: -1
Speed: -2
Speed: -3
10KA tbl 12C
1. During transitions, inputs may undershoot to -2.0V or overshoot to 5.75V for
periods shorter than 20ns. Otherwise, minimum DC input voltage is -0.5V.
2. Device inputs may be driven before VCCINT and VCCIO are powered.
3. Typical values are at VCC of 3.3 volts and ambient temperature of 25 C.
4. Guaranteed but not tested. Characterized initially, and after any design changes
which may affect these parameters.
5. Internal timing delays are based on characterization, and cannot be explicitly
tested. Internal timing parameters should be used for performance estimation
only.
6. Use AC Test Conditions set-up B for these parameters.
20 Apr. 2000:
Created new document
01 Dec. 2000:
Updated package availability and additional literature available
04 Jan. 2001:
Corrected table on AC Electrical Specifications
29 Mar. 2001:
Added Pin Configuration for the FBGA 256-pin package
AC Test Conditions
703
8.06k
35 pF
V
CCIO
OUTPUT
Includes jig
capacitance
703
8.06k
5 pF
V
CCIO
OUTPUT
Includes jig
capacitance
(A)
(B)
≤ 3ns
3.0V
90%
10%
GND
90%
10%
All Input Pulses
10KA drw 02
Notes to Tables
Revision History
A: Test fixture set-up A is for general testing.
B: Test fixture set-up B is for high Z testing (tZX#).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CL10K50SFC256-2 | FPGA |
| CL10K50SFC256-2X | FPGA |
| CL10K50SFC256-3 | FPGA |
| CL10K50SFC256-4 | FPGA |
| CL10K50SQC208-1 | FPGA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CL10K50SFC256-2 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA |
| CL10K50SFC256-2X | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA |
| CL10K50SFC256-3 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA |
| CL10K50SFC256-4 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA |
| CL10K50SQC208-1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA |
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