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參數(shù)資料
| 型號： | CL10K30ATC144-2 |
| 英文描述： | FPGA |
| 中文描述： | FPGA的 |
| 文件頁數(shù)： | 5/16頁 |
| 文件大?。?/td> | 178K |
| 代理商： | CL10K30ATC144-2 |
LIBERATOR CL10K30A
Page 13
AC Electrical Specifications cont.
EAB Timing Parameters[5]
Symbol
Parameter
Min
Max
Min
Max
Min
Max Unit
tEABAA
EAB Address Access Delay
9.7
11.6
16.2
ns
tEABRCCOMB EAB Asynchronous Read Cycle Time
9.7
11.6
16.2
ns
tEABRCREG EAB Synchronous Read Cycle Time
5.9
7.1
9.7
ns
tEABWP
EAB Write Pulse Width
3.8
4.5
5.9
ns
tEABWCCOMB EAB Asynchronous Write Cycle Time
4.0
4.7
6.3
ns
tEABWCREG EAB Synchronous Write Cycle Time
9.8
11.6
16.6
ns
tEABDD
EAB Data-in to Data-out Delay
9.2
11.0
16.1
ns
tEABDATACO
EAB Clock-to-output Delay Using Output
Registers
1.7
2.1
3.4
ns
tEABDATASU
EAB Data/Address Setup Time Using Input
Register
2.3
2.7
3.5
ns
tEABDATAH
EAB Data/Address Hold Time Using Input
Register
0.0
ns
tEABWESU EAB WE Setup When Using Input Register
3.3
3.9
4.9
ns
tEABWESH
EAB WE Hold Time When Using Input
Register
0.0
ns
tEABWDSU
EAB Data Setup Time to Falling Edge of
Write Pulse When Not Using Input Registers
3.2
3.8
5.0
ns
tEABWDH
EAB Data Hold Time After Falling Edge of
Write Pulse When Not Using Input Registers
0.0
ns
tEABWASU
EAB Address Setup Time to Rising Edge of
Write Pulse When Not Using Input Registers
3.7
4.4
5.1
ns
tEABWAH
EAB Address Hold Time After Falling Edge
of Write Pulse When Not Using Input
Registers
0.0
ns
tEABWO
EAB WE to Data Output Delay
6.1
7.3
11.3
ns
10KA tbl 11C
Speed: -1
Speed: -2
Speed: -3
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CL10K30ATC144-3 | FPGA |
| CL10K30ATI144-3 | FPGA |
| CL10K50SFC256-1 | FPGA |
| CL10K50SFC256-1X | FPGA |
| CL10K50SFC256-2 | FPGA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CL10K30ATC144-3 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA |
| CL10K30ATI144-3 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA |
| CL10K50SFC256-1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA |
| CL10K50SFC256-1X | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA |
| CL10K50SFC256-2 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA |
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