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14
201-0000-033 Rev 1.0, 6/2/99
CHRONTEL
CH5101A
that, the master may read another data byte and so on. In summary, a RESTART condition, followed by a DAB,
must be produced by the master before each of the RAB and before each of the data read events.
Figure 10
shows
two
consecutive alternating read cycles.
Figure 10: Alternating Read Cycle
If AutoInc = 1, then the address register will be incremented automatically and subsequent data bytes can be read
from successive registers, without providing a second RAB
Figure 11: Auto-increment Read Cycle
When the auto-increment mode is enabled (AutoInc is set to 1), the address register will continue incrementing for
each read cycle. When the content of the Address Register reaches 2A, it will wrap around and start from 00h again.
The auto increment sequence can be terminated by either a STOP or RESTART condition. The read operation can
be terminated with a “STOP” condition.
Figure 11
shows an auto-increment read cycle terminated by a STOP or
RESTART condition.The CH5101 contains 20 control registers each with a maximum of 8 usable bits to provide
access to basic video attribute control functions. These registers are accessible via the 2-bit serial bus (SD & SC).
The following sections describe the functions and the controls available through these registers.
SD
SC
1 - 8
RAB 1
9
10
ACK
Restart
Condition
Condition
Start
Condition
Stop
Master does
not acknowledge
1 - 7
Device
8
R/W*
9
ACK
CH5101
acknowledge
CH5101
acknowledge
1 - 8
Data 1
9
ACK
1 - 7
Device
8
R/W*
9
ACK
CH5101
acknowledge
I
2
C
10
Restart
Condition
1 - 8
RAB 2
9
10
ACK
Restart
Condition
1 - 7
Device ID
8
R/W*
9
ACK
CH5101
acknowledge
1 - 8
Data 2
9
ACK
1 - 7
Device ID
8
R/W*
9
ACK
CH5101
acknowledge
I
2
C
I
2
C
Master
does not
acknowledge
CH5101
acknowledge
Master
acknowledge
SD
SC
1 - 8
RAB n
9
10
ACK
Restart
Condition
Condition
Start
Condition
Stop
Master does
not acknowledge
just before Stop
condition
1 - 7
Device
8
R/W*
9
ACK
CH5101
acknowledge
CH5101
acknowledge
1 - 8
Data n
9
ACK
1 - 7
Device
8
R/W*
9
ACK
CH5101
acknowledge
1 - 8
Data
n+1
9
ACK
I
2
C
I
2
C