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參數(shù)資料
| 型號： | CH5001A-L |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | CMOS COLOR DIGITAL VIDEO CAMERA |
| 中文描述： | CMOS彩色數(shù)碼攝像機 |
| 文件頁數(shù)： | 11/34頁 |
| 文件大?。?/td> | 136K |
| 代理商： | CH5001A-L |
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CHRONTEL
CH5001A
201-0000-032 Rev 3.0, 6/2/99
11
R/W*
Due to the desired noise margin of 0.2V
DD
for the HIGH level, this input current limits the maximum value of R
P
.
The R
P
limit depends on V
DD
and is shown below:
R
P
>= (100 x V
DD
)/ I
input
(where: R
P
is in k
and I
input
is in
μ
A) Transfer Protocol
Both read and write cycles can be executed in Alternating and Auto-increment modes. Alternating mode expects a
register address prior to each read or write from that location (i.e., transfers alternate between address and data).
Auto-increment mode allows you to establish the initial register location, then automatically increments the register
address after each subsequent data access (i.e., transfers will be address, data, data, data...). A basic serial port
transfer protocol is shown in
Figure 5
and described below.
Figure 5: Serial Port Transfer Protocol
1. The transfer sequence is initiated when a high-to-low transition of SD occurs while SC is high; this is the
START condition. Transitions of address and data bits can only occur while SC is low.
2. The transfer sequence is terminated when a low-to-high transition of SD occurs while SC is high; this is the
STOP condition.
3. Upon receiving the first START condition, the CH5001 expects a Device Address Byte (DAB) from the
master device. The value of the device address is shown in the DAB data format below. Note that B[2:1] is
determined by the state of the AS pin (see
Table 1
for details).
4. After the DAB is received, the CH5001 expects a Register Address Byte (RAB) from the master. The
format of the RAB is shown in the RAB data format below (note that B7 is not used).
R/W
Read/Write Indicator
0:
Master device will write to the CH5001 at the register location specified by the address
AR[5:0]
1:
Master device will read from the CH5001 at the register location specified by the
address AR[5:0]. AutoInc Register Address Auto-Increment - to facilitate sequential
R/W of registers 1: Auto-Increment enabled (auto-increment mode).
Table 3. Device Address Byte (DAB)
B7
B6
B5
B4
B3
B2
B1
B0
1
0
0
0
1
AS*
AS
R/W
SD
SC
1 - 8
9
Data
1
ACK
acCH5001
Condition
Start
Condition
Stop
CH5001
acknowledge
1 - 8
Data n
9
acCH5001
1 - 7
Device ID
8
9
ACK
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