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參數(shù)資料
| 型號： | CH21FL-FREQ-OUT23 |
| 廠商： | CAL CRYSTAL LAB INC |
| 元件分類： | XO, clock |
| 英文描述： | CRYSTAL OSCILLATOR, CLOCK, 1.8 MHz - 100 MHz, CMOS/TTL OUTPUT |
| 文件頁數(shù)： | 1/1頁 |
| 文件大小： | 135K |
| 代理商： | CH21FL-FREQ-OUT23 |
34
Cal Crystal Lab, Inc. / Comclok, Inc. 800-333-9825
1156 North Gilbert Street Anaheim, CA 92801
OSC With Tri-State
PIN
CONNECTION
#1
“L”
“H” or Open
#2
GND
#3
Z
Output
#4
Vcc
Z: high impedance
CERAMIC SURFACE MOUNT OSCILLATORS
MODEL
CJ 3.3V SMD
MODEL
CH 5.0V SMD
Model
Operating Temperature Range
Frequency Range
Frequency Stability
Symmetry
Rise & Fall Time (Tr, Tf)
Logic “1”
Current Consumption
100ppm Standard, Optional Tolerances Available
CJ
CH
Output Load
Aging
Enable Condition (optional)
Reflow Condition
Enable - Logic “1” 2.0VDC Min
Disable - Logic “0” 0.5VDC Max
1.8000MHz ~ 100.000MHz
-10
oC ~ +70oC
5ns Max
1.8MHz to 36.0MHz : 15mA
36.0MHz to 70.0MHz : 25mA
70.0MHz to 100.0MHz : 40mA
1.8000MHz ~ 100.000MHz
100ppm Standard, Optional Tolerances Available
-10
oC ~ +70oC
Storage Temperature Range
-55
oC ~ +125oC
Supply Voltage
+ 3.3VDC
± 10%
1.8MHz to 32.0MHz : 10mA
32.0MHz to 50.0MHz : 18mA
50.0MHz to 70.0MHz : 20mA
+ 5.0VDC
± 10%
60/40 @ 50% Vcc HCMOS or TTL 1.4V
Optional Tolerances Available
60/40 @ 50% Vcc HCMOS or TTL 1.4V
Optional Tolerances Available
10ns Max
2.97VDC Min
4.5VDC Min
Logic “0”
0.33VDC Max
0.5VDC Max
1 to 10 TTL / 15pF
< 5ppm per year
Enable - Logic “1” 2.0VDC Min
Disable - Logic “0” 0.5VDC Max
+240
oC
± 5oC for 10 seconds
+150
oC
± 10oC for 1 to 2 minutes (preheating)
-55
oC ~ +125oC
CASE DIMENSIONS
RECOMMENDED LAND PATTERN
OSC Without Tri-State
PIN
CONNECTION
#1
N.C.
#2
GND
#3
OUTPUT
#4
VDD
PACKAGE DATA
Item
Package
Lid
Metal
Base
Ceramic
Sealing
Seam-weld
Terminal Plating
Gold
DIMENSIONS
Inches
(mm)
CL: including fixture and probe capacitance
OUTPUT WAVEFORM
TEST CIRCUIT
TAPE SPECIFICATIONS1,000 PCS. PER REEL (180MM DIA.)
Stand-by Current “0” Lev. at #1
10
A Max
NA
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