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參數(shù)資料
| 型號： | CG3040-9 |
| 元件分類： | 電源模塊 |
| 英文描述： | 3-OUTPUT 25 W DC-DC REG PWR SUPPLY MODULE |
| 文件頁數(shù)： | 6/16頁 |
| 文件大?。?/td> | 283K |
| 代理商： | CG3040-9 |
Board Mountable
DC-DC Converters
G Series
Edition 5/5.2000
14/16
Description of Options
D
Voltage monitor and reset sequencer including
– Generation of start-up and reset control signals
(/PWD, /SDW, /RST, CT1, CT2)
– Output voltage monitor with diagnostics
/FAIL, /SRQ)
Start-up and reset control signals
These control signals can be used in micro controller, micro
processor or sequencer applications where start-up and
shut-down sequences need to be adapted to the status of
their supply voltage. The pins allocated to this option are:
The /PDW (power down) input, e.g. the AC-fail signal of a
front-end, the /SDW (shut-down) and the /RST (reset) out-
puts, the CT1 and CT2 adjustment pins.
All secondary inputs and outputs are electrically isolated
from the input circuitry and referenced to Go. In applications
where this isolation is essential, opto-couplers are recom-
mended to provide the signal link between primary and sec-
ondary side.
Example of a system configuration: A central AC-DC con-
verter delivers a main DC bus voltage. On local electronic
boards, decentralized DC-DC converters stabilize and con-
dition the main DC voltage to one or several specific DC
voltages.
If the AC mains fails and the AC-DC converter delivers an
AC fail signal, it can be used to trigger a predefined signal
sequence between the G series DC-DC converter and the
microprocessor (or other circuitry).
Fig. 25
Example of system architecture
CT1, CT2 Timing control
The delays
t1 and t2 can be defined by capacitors con-
nected between CT1 and CT2 to Go according to the for-
mula:
t1 = k0 + k1 CT1; t2 = k0 + k1 CT2
Table 16: Parameters for t1 and t2
Parameter
min.
typ.
max.
Units
k0
10
20
30
s
k1
95
100
105
s/nF
CT1; CT2
0
2500
nF
/SDW (/shut down), /RST (/reset)
Open collector outputs with internal pull-up resistors of
4.7 k typ. connected to Vo1.
/PDW (/power down)
Digital input with internal pull-up resistor of 6.8 k
typ. con-
nected to Vo1+.
Table 18: Input/output data of /PDW, /SDW, /RST
Parameter Condition
min.
max.
Units
Isink /SDW
U/SDW <0.6 V
48
mA
Isink /RST
U/RST <0.6 V
48
U/PDW High
0.7
Uo1
U/PDW Low
0.3
Uo1
Table 17: Timing tolerance for t3 and t4
Delay
min.
max.
Units
t3
25
27.5
ms
t4
200
220
Important: No voltage higher than
Uo1 should be applied
to /PDW, /SDW and /RST otherwise the unit may be
damaged.
Functional description
After the detection of a mains failure (/PDW) a routine to
save volatile memory can be started by /SDW after the time
t1, before the microprocessor is reset by /RST, after t2.
At start-up /SDW will be released before /RST goes high (
t3,
t4). Both delays, t1 and t2, can individually be adjusted by a
capacitor in the range of 20
s to 250 ms. The delays t
3 and
t4 are fixed and can not be adjusted.
The /SDW and the /RST outputs are not only controlled by
the /PDW input, but also by the voltage of the main output. If
Uo1 falls below 4.58 V ±2% /SDW, /RST are immediately
taken low independently of the status of the /PDW. At start-
up the /SDW, /RST signals will only be released if
Uo1 is
higher than 4.58 V
±2%.
In any case a /SDW will be followed by an /RST.
/PDW
Uo1
/SDW
/RST
t/PDW < t1
t1 < t/PDW < t1 + t2
t/PDW > t1 + t2
Uo1 < 4.58 V
t/PDW
4.58 V
t1
t2
t3
t4
t1
t2
t3
t4
t3
t4
11024
Fig. 26
Timing of the control signals
G-family
DC-DC
Converter
Micro-
processor
Front-End
AC-DC
Converter
Opto-coupler
/SDW
/RST
/PDW
+
–
AC-Fail signal
+ –
≈
1
1013
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