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參數(shù)資料
| 型號(hào)： | CE77 |
| 廠商： | Fujitsu Limited |
| 英文描述： | Semicustom CMOS Embedded array |
| 中文描述： | 半定制嵌入式陣列的CMOS |
| 文件頁數(shù)： | 1/24頁 |
| 文件大小： | 167K |
| 代理商： | CE77 |
DS06-20112-2E
FUJITSU SEMICONDUCTOR
DATA SHEET
Copyright2002-2007 FUJITSU LIMITED All rights reserved
Semicustom
CMOS
Embedded array
CE77 Series
■
DESCRIPTION
The CE77 series 0.25
μ
m CMOS embedded array is a line of highly integrated CMOS ASICs featuring high speed
and low power consumption at the same time.
CE77 series is available in 15 frames with the enhanced lineup of 470 K to 6980 K gates.
■
FEATURES
Technology
Supply voltage
Junction temperature range :
40
°
C to
+
125
°
C
Gate delay time : t
pd
=
33 ps (2.5 V, inverter cell High Speed type, F/O
=
1, No load)
Gate power consumption : 0.02
μ
W/MHz (1.5 V, F/O
=
1, No load)
High-load driving capability : I
OL
=
2 mA/4 mA/8 mA/12 mA mixable
Output buffer cells with noise reduction circuits
Inputs with on-chip input pull-up/pull-down resistors (25 k
typical) and bidirectional buffer cells
Buffer cells dedicated to crystal oscillator
Special interface (P-CML, LVDS, T-LVTTL, SSTL, PCI, USB, GTL
+
, and others including those under
development)
IP macros (CPU, PCI, USB, IrDA, PLL, DAC, ADC, and others including those under development)
Capable of incorporating compiled cells (RAM/ROM/FIFO/Delay line, and others.)
Configurable internal bus circuits
Advanced hardware/software co-design environment
Support for static timing sign-off
Dramatically reducing the time for generating test vectors for timing verification and the simulation time
Hierarchical design environment for supporting large-scale circuits
Simulation (before layout) considering the input slew rate and detailed RC delay calculation (after layout) ,
supporting development with minimized timing trouble after trial manufacture
: 0.25
μ
m silicon-gate CMOS, 3- to 4-layer wiring
:
+
2.5 V
±
0.2 V (normal) to
+
1.5 V
±
0.1 V
(Continued)
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