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參數(shù)資料
| 型號： | CDP1822C3 |
| 廠商： | Intersil Corporation |
| 英文描述： | High-Reliability CMOS 256-Word x 4-Bit LSI Static RAM |
| 中文描述： | 高可靠性的CMOS 256字× 4位LSI的靜態(tài)存儲器 |
| 文件頁數(shù)： | 1/5頁 |
| 文件大?。?/td> | 27K |
| 代理商： | CDP1822C3 |
6-19
March 1997
CDP1822C/3
High-Reliability CMOS
256-Word x 4-Bit LSI Static RAM
Features
For Applications in Aerospace, Military, and Critical
Industrial Equipment
Interfaces Directly with CDP1802 Microprocessor
Very Low Operating Current
- At V
DD
= 5V and Cycle Time = 1
μ
s . . . . . . 4mA (Typ)
Static CMOS Silicon-On-Sapphire Circuitry
- CD4000 Series Compatible
Industry Standard Pinout
Two Chip Select Inputs - Simple Memory Expansion
Memory Retention for Standby. . . . . . . . . . . . . 2V (Min)
Battery Voltage
Single Power Supply Operation . . . . . . . . . . 4V to 6.5V
High Noise Immunity 30% of V
DD
. . . . . . . . . 4V to 6.5V
Output Disable for Common I/O Systems
Three-State Data Output for Bus Oriented Systems
Separate Data Inputs and Outputs
Latch-Up-Free Transient Radiation Tolerance
Description
The CDP1822C/3 is a 256 word by 4-bit random access
memory designed for use in memory systems where high
speed, low operating current, and simplicity in use are
desirable. The CDP1822 features high speed and excellent
noise immunity. It has separate data inputs and outputs and
utilizes a single power supply of 4V to 6.5V.
Two Chip Select inputs simplify system expansion. An output
Disable control provides Wire-OR-capability and is also
useful in common Input/Output systems. The Output Disable
input allows this RAM to be used in common data Input/Out-
put systems by forcing the output into a high impedance
state during a write operation independent of the Chip Select
input condition. The output assumes a high impedance state
when the Output Disable is at high level or when the chip is
deselected by CS1 and/or CS2.
The high noise immunity of the CMOS technology is
preserved in this design. For TTL interfacing at 5V operation,
excellent system noise margin is preserved by using an
external pull-up resistor at each input.
Pinout
CDP1822C/3 (SBDIP)
TOP VIEW
Ordering Information
PACKAGE
TEMP. RANGE
-55
o
C to +125
o
C
PART
NUMBER
PKG. NO.
SBDIP
CDP1822CD3
D22.4A
1
11
10
9
8
7
6
5
3
2
4
22
12
13
14
15
16
17
18
19
21
20
A2
A1
A0
A5
A6
A7
DI1
V
SS
DO1
DI2
A4
CS1
O. D.
CS2
R/W
DO4
DI4
DO3
DI3
DO2
A3
V
DD
OPERATIONAL MODES
MODE
INPUTS
OUTPUT
CHIP
SELECT
1
(CS1)
CHIP
SELECT
2
(CS2)
OUTPUT
DISABLE
(OD)
READ/
WRITE
(R/W)
Read
0
1
0
1
Read
Write
0
1
0
0
Data In
Write
0
1
1
0
High
Impedance
Standby
1
X
X
X
High
Impedance
Standby
X
0
X
X
High
Impedance
Output
Disable
X
X
1
X
High
Impedance
Logic 1 = High, Logic 0 = Low, X = Don’t Care
File Number
2981.1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
|
Copyright
Intersil Corporation 1999
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CDP1822 | 256-Word x 4-Bit LSI Static RAM |
| CDP1822CD | 256-Word x 4-Bit LSI Static RAM |
| CDP1822CDX | 256-Word x 4-Bit LSI Static RAM |
| CDP1822CE | 256-Word x 4-Bit LSI Static RAM |
| CDP1822CEX | 256-Word x 4-Bit LSI Static RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CDP1822CD | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:256-Word x 4-Bit LSI Static RAM |
| CDP1822CD/3 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x4 SRAM |
| CDP1822CDX | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:256-Word x 4-Bit LSI Static RAM |
| CDP1822CE | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:256-Word x 4-Bit LSI Static RAM |
| CDP1822CEX | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:256-Word x 4-Bit LSI Static RAM |
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