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參數(shù)資料
| 型號： | CDCU2A877ZQL |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 1.8-V PHASE LOCK LOOP CLOCK DRIVER |
| 中文描述： | 的1.8 V鎖相環(huán)時(shí)鐘驅(qū)動器 |
| 文件頁數(shù)： | 1/14頁 |
| 文件大?。?/td> | 362K |
| 代理商： | CDCU2A877ZQL |
www.ti.com
FEATURES
1.8-V/1.9-V Phase Lock Loop Clock Driver for
Double Data Rate ( DDR II ) Applications
Spread Spectrum Clock Compatible
Operating Frequency: 125 MHz to 410 MHz
Application Frequency: 160 MHz to 410 MHz
Low Jitter (Cycle-Cycle):
±
40 ps
Low Output Skew: 35 ps
Stabilization Time <6
μ
s
Distributes One Differential Clock Input to 10
Differential Outputs
DESCRIPTION
The CDCU2A877 is a high-performance, low-jitter, low-skew, zero-delay buffer that distributes a differential clock
input pair (CK, CK) to 10 differential pairs of clock outputs (Yn, Yn) and to one differential pair of feedback clock
outputs (FBOUT, FBOUT). The clock outputs are controlled by the input clocks (CK, CK), the feedback clocks
(FBIN, FBIN), the LVCMOS control pins (OE, OS), and the analog power input (AV
). When OE is low, the
clock outputs, except FBOUT/FBOUT, are disabled while the internal PLL continues to maintain its locked-in
frequency. OS (output select) is a program pin that must be tied to GND or V
DD
. When OS is high, OE functions
as previously described. When OS and OE are both low, OE has no affect on Y7/Y7, they are free running.
When AV
DD
is grounded, the PLL is turned off and bypassed for test purposes.
When both clock inputs (CK, CK) are logic low, the device enters in a low power mode. An input logic detection
circuit on the differential inputs, independent from input buffers, detects the logic low level and performs in a low
power state where all outputs, the feedback, and the PLL are off. When the clock inputs transition from being
logic low to being differential signals, the PLL turns back on, the inputs and the outputs are enabled, and the
PLL obtains phase lock between the feedback clock pair (FBIN, FBIN) and the clock input pair (CK, CK) within
the specified stabilization time.
CDCU2A877
SCAS827–AUGUST 2006
1.8-V PHASE LOCK LOOP CLOCK DRIVER
High-Drive Version of CDCUA877
52-Ball mBGA (MicroStar Junior BGA,
0,65-mm pitch)
External Feedback Pins ( FBIN, FBIN ) are
Used to Synchronize the Outputs to the Input
Clocks
Meets or Exceeds CUA877/CUA878
Specification PLL Standard for
PC2-3200/4300/5300/6400
Fail-Safe Inputs
The CDCU2A877 is able to track spread spectrum clocking (SSC) for reduced EMI. This device operates from
0
°
C to 70
°
C.
AVAILABLE OPTIONS
T
A
52-Ball BGA
(1)
CDCU2A877ZQL
0
°
C to 70
°
C
(1)
For the most current package and ordering information, see the
Package Option Addendum at the end of this document, or see the
TI website at
www.ti.com
.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
MicroStar Junior is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright 2006, Texas Instruments Incorporated
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CDCU2A877ZQLR | 功能描述:時(shí)鐘驅(qū)動器及分配 1.8V Ph-Lock Loop Clock Driver RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| CDCU2A877ZQLT | 功能描述:時(shí)鐘驅(qū)動器及分配 1.8V Ph-Lock Loop Clock Driver RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| CDCU877 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:1.8V PHASE LOCK LOOP CLOCK DRIVER |
| CDCU877A | 制造商:TI 制造商全稱:Texas Instruments 功能描述:1.8V PHASE LOCK LOOP CLOCK DRIVER |
| CDCU877AGQL | 制造商:TI 制造商全稱:Texas Instruments 功能描述:1.8V PHASE LOCK LOOP CLOCK DRIVER |
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