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參數資料
| 型號： | CDC2587 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Octal Divided -by-2 Circuit/Clock Driver(3.3V鎖相環(huán)時鐘驅動器(三態(tài)輸出)) |
| 中文描述： | 八路分裂的× 2電路/時鐘驅動器（3.3鎖相環(huán)時鐘驅動器（三態(tài)輸出）） |
| 文件頁數： | 1/8頁 |
| 文件大?。?/td> | 163K |
| 代理商： | CDC2587 |
CDC2587
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
WITH 3-STATE OUTPUTS
SCAS560B – DECEMBER 1995 – REVISED JULY 1996
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Low-Output Skew and Jitter for Clock
Distribution and Synchronization
Operates at 3.3-V V
CC
Distributes One Clock Input to 16 Outputs
Four Select Inputs Configure Output
Frequency
Internal Loop Filter Eliminates the Need for
External RC Network
Dedicated External Feedback Output and
Input for Phase Synchronization With the
Clock Input
Applications for Synchronous DRAM,
High-Speed Microprocessors, and SSTL_3
Applications
LVTTL- or SSTL_3-Compatible Inputs and
Outputs
Distributed V
CC
and GND Pin Configuration
Minimize High-Speed Switching Noise
Meets SSTL_3 Class 1 and 2 Specifications
Packaged in 56-Pin Plastic Small-Outline
Package
description
The CDC2587 is a high-performance, low-skew,
low-jitter, phase-lock loop (PLL) clock driver. It
uses a PLL to precisely align, in both frequency
and phase, the clock output signals to the clock
input (CLKIN) signal. The CDC2587 operates at
3.3-V
V
CC
and
provides
SSTL_3-compatible inputs and outputs. The
CDC2587
operates
16.67 MHz to 150 MHz, and is ideally suited for
high-speed microprocessor and synchronous
DRAM applications. The CDC2587 provides
integrated 25-
series damping resistors to
improve signal integrity.
LVTTL-
or
at
frequencies
from
A dedicated feedback output (FBOUT) is used to synchronize the output clocks in frequency and phase to the
CLKIN reference. Four banks of four outputs (1Yn, 2Yn, 3Yn, 4Yn) are configured to operate at specified ratios
of the input frequency by four select (SELn) inputs . Selectable ratios of the input frequency are 1X, 2X, 3X, 1/2X,
and 1/3X.
Copyright
1996, Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
DGG PACKAGE
(TOP VIEW)
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CLKIN
V
REF
FBIN
V
CC
FBOUT
GND
V
CC
1Y0
1Y1
GND
V
CC
1Y2
1Y3
GND
V
CC
2Y0
2Y1
GND
V
CC
2Y2
2Y3
GND
V
CC
GND
SEL0
SEL1
SEL2
SEL3
V
CC
GND
AV
CC
AGND
AV
CC
AGND
V
CC
4Y0
4Y1
GND
V
CC
4Y2
4Y3
GND
V
CC
3Y0
3Y1
GND
V
CC
3Y2
3Y3
GND
V
CC
GND
RESET
TEST
OE
GND
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
P
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相關代理商/技術參數 |
參數描述 |
|---|---|
| CDC2587DGGR | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Sixteen Distributed-Output Clock Driver |
| CDC-25PF | 制造商:HRS 制造商全稱:HRS 功能描述:CD CRIMP TYPE CONNECTOR |
| CDC-25SF | 制造商:HRS 制造商全稱:HRS 功能描述:CD CRIMP TYPE CONNECTOR |
| CDC303 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:OCTAL DIVIDE-BY-2 CIRCUIT/CLOCK DRIVER |
| CDC303D | 功能描述:時鐘驅動器及分配 1-8,Divide-By-2 Clock Driver RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
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