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參數(shù)資料
| 型號： | CDB8421 |
| 廠商： | Cirrus Logic Inc |
| 文件頁數(shù)： | 1/17頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR CS8421 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 音頻，采樣率轉(zhuǎn)換器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | CS8421，CS8406，CS8416 |
| 主要屬性： | 帶數(shù)字音頻發(fā)射器和接收器的采樣率轉(zhuǎn)換器 |
| 次要屬性： | S/PDIF 接口 |
| 已供物品： | 板，CD |
| 產(chǎn)品目錄頁面： | 759 (CN2011-ZH PDF) |
| 相關(guān)產(chǎn)品： | 598-1730-ND - IC SAMPLE RATE CONVERTER 20QFN 598-1126-5-ND - IC SAMPLE RATE CONVERTER 20TSSOP |
| 其它名稱： | 598-1018 |
Copyright
Cirrus Logic, Inc. 2012
(All Rights Reserved)
32-bit, 192-kHz Asynchronous Sample Rate Converter
Features
175 dB Dynamic Range
–140 dB THD+N
No Programming Required
No External Master Clock Required
Supports Sample Rates up to 211 kHz
Input/Output Sample Rate Ratios of 7.5:1 to 1:8
Master Clock Support for 128 x Fs, 256 x Fs,
384 x Fs, and 512 x Fs (Master Mode)
16-, 20-, 24-, or 32-bit Data I/O
32-bit Internal Signal Processing
Dither Automatically Applied and Scaled to
Output Resolution
Flexible 3-wire Serial Digital Audio Input and
Output Ports
Master and Slave Modes for Both Input and
Output
Bypass Mode
Time Division Multiplexing (TDM) Mode
Attenuates Clock Jitter
Multiple Device Outputs are Phase Matched
Linear Phase FIR Filter
Automatic Soft Mute/Unmute
+2.5 V Digital Supply (VD)
+3.3 V or 5.0 V Digital Interface (VL)
Space-saving 20-pin TSSOP and QFN
Packages
The CS8421 supports sample rates up to 211 kHz and
is available in 20-pin TSSOP and QFN packages in both
Commercial (-10° to +70°C) and Automotive (-40° to
+85°C and -40° to +105°C) grades. The CDB8421 Cus-
tomer Demonstration board is also available for device
evaluation and implementation suggestions. See “Or-
dering Information” on page 35 for complete details.
Serial
Audio
Input
Time
Varying
Digital
Filters
BYPASS
Digital
PLL
Clock
Generator
ILRCK
ISCLK
SDIN
Sync Info
Data
Serial
Audio
Output
OLRCK
OSCLK
SDOUT
XTI
XTO
SRC_UNLOCK
2.5 V (VD)
GND
RST
Sync Info
Data
Level Translators
TDM_IN
MS_SEL
SAIF
SAOF
Serial
Port
Mode
Decoder
Level
Tr
anslat
or
s
L
evel
Tra
n
sl
a
tors
MCLK_OUT
3.3 V or 5.0 V (VL)
JULY ‘12
DS641F6
CS8421
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