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參數(shù)資料
| 型號： | CDB5368 |
| 廠商： | Cirrus Logic Inc |
| 文件頁數(shù)： | 8/19頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR CS5368 192KHZ ADC |
| 標(biāo)準(zhǔn)包裝： | 1 |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 192k |
| 數(shù)據(jù)接口： | 串行 |
| 輸入范圍： | ±0.3 V |
| 工作溫度： | -40°C ~ 85°C |
| 已用 IC / 零件： | CS5368 |
| 已供物品： | 板，線纜 |
| 產(chǎn)品目錄頁面： | 756 (CN2011-ZH PDF) |
| 相關(guān)產(chǎn)品： | CS5368-DQZ-ND - IC ADC 8CH 114DB 216KHZ 48-LQFP CS5368-CQZR-ND - IC ADC 8CH 114DB 216KHZ 48-LQFP 598-1090-ND - IC ADC 8CH 114DB 216KHZ 48-LQFP |
| 其它名稱： | 598-1157 |
16
DS624F4
CS5368
SERIAL AUDIO INTERFACE - TDM TIMING
The serial audio port is a three-pin interface consisting of SCLK, LRCK and SDOUT.
Logic "0" = GND = 0 V; Logic "1" = VLS; CL = 20 pF, timing threshold is 50% of VLS.
Notes:
1.
TDM Quad-Speed Mode only specified to operate correctly at VLS
≥ 3.14 V.
2.
Duty cycle of generated SCLK depends on duty cycle of received MCLK as specified under “System
3.
CLKMODE functionality described in Section 4.6.3
4.
In Slave Mode, the SCLK/LRCK ratio can be set according to preference; chip performance is guaran-
teed only when using the ratios in Section 4.7 Master and Slave Clock Frequencies on page 25.
Figure 4. TDM Timing
Parameter
Symbol
Min
Typ
Max
Unit
Sample Rates
Single-Speed Mode
Double-Speed Mode
Quad-Speed Mode1
-
2
54
108
-
54
108
216
kHz
Master Mode
SCLK Frequency
SCLK Period
1/(256*216 kHz)
SCLK Duty Cycle (Note 2)
(CLKMODE = 0)(Note 3)
(CLKMODE = 1)(Note 3)
tPERIOD
tHIGH1
256*Fs
18
40
28
-
50
33
256*Fs
-
60
38
Hz
ns
%
FS setup
before SCLK rising (Single-Speed Mode)
FS setup
before SCLK rising (Double-Speed Mode)
FS setup
before SCLK rising (Quad-Speed Mode)
FS width
in SCLK cycles
tSETUP1
tHIGH2
20
18
5
128
-
128
ns
-
SDOUT setup
before SCLK rising
SDOUT hold
after SCLK rising
tSETUP2
tHOLD2
5
-
ns
Slave Mode
SCLK Frequency (Note 4)
SCLK Period
1/(256*216 kHz)
SCLK Duty Cycle
tPERIOD
tHIGH1
-
18
28
256*Fs
-
65
Hz
ns
%
FS setup
before SCLK rising (Single-Speed Mode)
FS setup
before SCLK rising (Double-Speed Mode)
FS setup
before SCLK rising (Quad-Speed Mode)
FS width
in SCLK cycles
tSETUP1
tHIGH2
20
10
1
-
244
ns
-
SDOUT setup
before SCLK rising
SDOUT hold
after SCLK rising
tSETUP2
tHOLD2
5
-
ns
FS
SDOUT
SCLK
data
t
HOLD2
t
SETUP2
t
SETUP1
new frame
data
t
PERIOD
t
HIGH1
t
HIGH2
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CDB5374 | 功能描述:音頻 IC 開發(fā)工具 2-Ch DS Modulator & Hydrophone Demo Brd RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Kits 類型:Audio Amplifiers 工具用于評估:TAS5614L 工作電源電壓:12 V to 38 V |
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| CDB5376Z | 制造商:Cirrus Logic 功能描述:PB-FREE EVAL BD LOW-POWER, MULTICH DECIMATION FILTER - Bulk |
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| CDB5378Z | 制造商:Cirrus Logic 功能描述:PB-FREE EVAL BD LOW-POWER, MULTICH DECIMATION FILTER - Bulk |
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