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參數(shù)資料
| 型號(hào)： | CDB4354 |
| 廠商： | Cirrus Logic Inc |
| 文件頁(yè)數(shù)： | 7/24頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | EVAL BOARD 5V DAC 2VRMS LINEDVR |
| 標(biāo)準(zhǔn)包裝： | 1 |
| DAC 的數(shù)量： | 1 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 192k |
| 數(shù)據(jù)接口： | I²S，串行 |
| DAC 型： | 電壓 |
| 工作溫度： | -40°C ~ 85°C |
| 已供物品： | 板 |
| 已用 IC / 零件： | CS4354 |
| 產(chǎn)品目錄頁(yè)面： | 757 (CN2011-ZH PDF) |
| 其它名稱： | 598-1809 CDB4354-ND |
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DS895F2
15
CS4354
Figure 7. De-Emphasis Curve, Fs = 44.1 kHz
Note:
De-emphasis is only available in Single-Speed Mode.
4.5
Internal High-Pass Filter
The CS4354 includes an internal digital high-pass filter. This filter prevents a constant digital offset from cre-
ating a DC voltage on the analog output pins. The filter’s corner frequency is well below the audio band; see
“Combined Digital and On-Chip Analog Filter Characteristics” on page 7 for filter specifications.
4.6
Digital Interface Format
The device accepts audio samples in the industry standard IS format only.
For an illustration of the required relationship between the LRCK, SCLK and SDIN, see Figure 6 on page
14. SDIN is valid on the rising edge of SCLK. For more information about serial audio formats, refer to Cirrus
Logic Application Note AN282: The 2-Channel Serial Audio Interface: A Tutorial, available at
4.7
Internal Power-On Reset
The CS4354 features an internal power-on reset (POR) circuit. This circuit monitors the VA supply and au-
tomatically asserts or releases an internal reset of the DAC’s digital circuitry when the supply reaches de-
fined thresholds (see “Internal Power-On Reset Threshold Voltages” on page 10). No external clocks are
required for the POR circuit to function.
Figure 8. Internal Power-On Reset Circuit
Gain
dB
-10dB
0dB
Frequency
T2 = 15 s
T1=50 s
F1
F2
3.183 kHz
10.61 kHz
Power-On Reset
Circuit
VA
GND
reset
(internal)
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