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參數(shù)資料
| 型號： | CDB3318 |
| 廠商： | Cirrus Logic Inc |
| 文件頁數(shù)： | 15/17頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR CS3318 VOL CTRL |
| 標準包裝： | 1 |
| 主要目的： | 音頻，音量控制 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | CS3318 |
| 主要屬性： | 8 個單端模擬輸入和輸出，USB 或 RS232 接口 |
| 次要屬性： | 圖形用戶界面 |
| 已供物品： | 板 |
| 產(chǎn)品目錄頁面： | 759 (CN2011-ZH PDF) |
| 相關(guān)產(chǎn)品： | CS3318-CQZR-ND - IC ANLG VOL CTRL 8CH 48-LQFP 598-1180-ND - IC ANLG VOL CTRL 8CH DGTL 48LQFP |
| 其它名稱： | 598-1497 |
7
Precision Edge
SY89827L
Micrel, Inc.
M9999-073010
hbwhelp@micrel.com or (408) 955-1690
VCCI = 3.3V ±5%, VCCO = 1.8V ±10%, TA = –40°C to +85°C, all outputs loaded, unless noted.
Symbol
Parameter
Condition
Min
Typ
Max
Units
fMAX
Maximum Toggle Frequency
Note 2
500
MHz
tPD
Differential Propagation Delay
Note 3
1.0
1.3
1.5
ns
VPP
Minimum Input Swing,
Note4
HSTL
200
mV
PECL
150
mV
tSW
Switchover Time
CLK_SEL-to-Q
1.6
2.0
ns
SEL-to-Q
1.4
1.75
ns
tJITTER
RMSPhaseJitter
Output:622MHz
IntegrationRange:12kHz-20MHz
186
fs
tS(OE)
Output Enable Set-Up Time
Note 5
1.0
ns
tH(OE)
Output Enable Hold Time
Note 5
0.5
ns
tskew
Within Device Skew
Note6
0°C to +85°C
25
50
ps
–40°C
35
75
ps
Part-to-Part Skew
Note 7
400
ps
tr, tf
Output Rise/Fall Times
450
700
ps
(20% to 80%)
Note 1. Outputsloadedwith50-t-ground.
Note 2. fMAXisdefinedasthemaximumtogglefrequency,measuredwitha750mVLVPECL/HSTLinput.HSTLoutputswingis>400mV.
Note 3. Differential propagation delay is defined as the delay from the crossing point of the differential input signals to the crossing point of the
differential output signals.
Note4. The VPP(min.)isdefinedastheminimuminputdifferentialvoltagewhichwillcausenoincreaseinthepropagationdelay.
Note 5. OEset-uptimeisdefinedwithrespecttotherisingedgeoftheclock.OEHIGH-to-LOWtransitionensuresoutputsremaindisabledduringthe
next clock cycle. OE LOW-to-HIGH transition enables normal operation of the next input clock.
Note6. Thewithin-deviceskewisdefinedastheworstcasedifferencebetweenanytwosimilardelaypathswithinasingledeviceoperatingatthe
same voltage and temperature. This parameters includes within bank skew and bank-to-bank skew.
Note 7. Thepart-to-partskewisdefinedastheabsoluteworstcasedifferencebetweenanytwodelaypathsonanytwodevicesoperatingatthesame
voltage and temperature.
AC ELECTRICAL CHARACTERISTICS(NOTE1)
PHASE NOISE
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
-200
10
100
1K
10K
100K
1M
10M
100M
OFFSETFREQUENCY(Hz)
NOISEPOWER(dBc/Hz)
PhaseNoisePlot:622MHz@3.3V
RMS Phase Jitter (Random)
12kHzto20MHz:186fs(Typical)
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